Cypress CY7C1520KV18 manuals
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Cypress CY7C1520KV18 Manual
30 pages 1.18 Mb
72-Mbit DDR-II SRAM 2-Word Burst ArchitectureCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Features Configurations Functional Description 2 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Logic Block Diagram (CY7C1516KV18) Logic Block Diagram (CY7C1527KV18)4M x 8 Array 4M x 8 Array 4M x 9 Array 4M x 9 Array Document Number: 001-00437 Rev. *E Page 3 of 30 3 Logic Block Diagram (CY7C1518KV18)Logic Block Diagram (CY7C1520KV18)2M x 18 Array 2M x 18 Array 1M x 36 Array 1M x 36 Array 4 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 5 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 6 CY7C1516KV18, CY7C1527KV187 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV188 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV1815 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18TAP Controller Block Diagram TAP Electrical Characteristics 16 CY7C1516KV18, CY7C1527KV1818 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Boundary Scan Order Power Up Sequence in DDR-II SRAM 19 VVPower Up Sequence PLL Constraints / 20 CY7C1518KV18, CY7C1520KV1827 CY7C1516KV18, CY7C1527KV1829 Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180[+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page
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