CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18
72-Mbit DDR-II SRAM 2-Word Burst Architecture
Features
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■333 MHz Clock for High Bandwidth
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■Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz
■Two Input Clocks (K and K) for precise DDR Timing
❐SRAM uses rising edges only
■Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
■Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
■Synchronous Internally
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■Operates similar to
■1.8V Core Power Supply with HSTL Inputs and Outputs
■Variable Drive HSTL Output Buffers
■Expanded HSTL Output Voltage
❐Supports both 1.5V and 1.8V IO supply
■Available in
■Offered in both
■JTAG 1149.1 compatible Test Access Port
■Phase Locked Loop (PLL) for Accurate Data Placement
Functional Description
The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 are 1.8V Synchronous Pipelined SRAM equipped with
Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with
Configurations
CY7C1516KV18 – 8M x 8
CY7C1527KV18 – 8M x 9
CY7C1518KV18 – 4M x 18
CY7C1520KV18 – 2M x 36
Table 1. Selection Guide
Description |
| 333 MHz | 300 MHz | 250 MHz | 200 MHz | 167 MHz | Unit |
Maximum Operating Frequency |
| 333 | 300 | 250 | 200 | 167 | MHz |
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Maximum Operating Current | x8 | 510 | 480 | 420 | 370 | 340 | mA |
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| x9 | 510 | 480 | 420 | 370 | 340 |
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| x18 | 520 | 490 | 430 | 380 | 340 |
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| x36 | 640 | 600 | 530 | 450 | 400 |
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Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document Number: |
| Revised March 30, 2009 |
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