CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Switching Characteristics (continued)
Over the Operating Range [20, 21]
Cypress | Consortium |
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| Description | 333 MHz | 300 MHz | 250 MHz | 200 MHz | 167 MHz | Unit | ||||||||||||||||
Parameter | Parameter |
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| Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | |||||||||||||
Output Times |
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tCO | tCHQV | C/C | Clock Rise (or K/K in single | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.50 | ns | |||||||||||||||
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| clock mode) to Data Valid |
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tDOH | tCHQX |
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Data Output Hold after Output C/C |
| – | – | – | – | – | ns | ||||||||||||||||||||||
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| Clock Rise (Active to Active) |
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tCCQO | tCHCQV |
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| Clock Rise to Echo Clock Valid | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.50 | ns | ||||||||||||||
C/C | |||||||||||||||||||||||||||||
tCQOH | tCHCQX |
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Echo Clock Hold after C/C | Clock | – | – | – | – | – | ns | ||||||||||||||||||||||
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| Rise |
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tCQD | tCQHQV | Echo Clock High to Data Valid | – | 0.25 | – | 0.27 | – | 0.30 | – | 0.35 | – | 0.40 | ns | ||||||||||||||||
tCQDOH | tCQHQX | Echo Clock High to Data Invalid | – | – | – | – | – | ns | |||||||||||||||||||||
tCQH | tCQHCQL |
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| HIGH [23] | 1.25 | – | 1.40 | – | 1.75 | – | 2.25 | – | 2.75 | – | ns | |||||||
Output Clock (CQ/CQ) | |||||||||||||||||||||||||||||
tCQHCQH |
| tCQHCQH |
| CQ Clock Rise to |
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| Clock Rise | 1.25 | – | 1.40 | – | 1.75 | – | 2.25 | – | 2.75 | – | ns | |||||||||||
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| (rising edge to rising edge) [23] |
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tCHZ | tCHQZ |
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Clock (C/C) | Rise to | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.45 | – | 0.50 | ns | |||||||||||||||||
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tCLZ | tCHQX1 |
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| Rise to |
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Clock (C/C) | – | – | – | – | – | ns | |||||||||||||||||||||||
PLL Timing |
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tKC Var | tKC Var | Clock Phase Jitter | – | 0.20 | – | 0.20 | – | 0.20 | – | 0.20 | – | 0.20 | ns | ||||||||||||||||
tKC lock | tKC lock | PLL Lock Time (K, C) | 20 | – | 20 | – | 20 | – | 20 | – | 20 | – | μs | ||||||||||||||||
tKC Reset | tKC Reset | K Static to PLL Reset | 30 | – | 30 | – | 30 | – | 30 | – | 30 | – | ns |
Notes
23.These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production.
24.tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from
25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: | Page 24 of 30 |
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