CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the
PLL
These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 μs of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 μs after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in
Application Example
Figure 1 shows two
Figure 1. Application Example
SRAM#1 ZQ
DQCQ/CQ#
A LD# R/W# C C# K K#
| DQ |
| |
BUS | Addresses |
| |
MASTER | Cycle Start# |
| |
(CPU | R/W# |
| |
or | Return CLK | Vterm = 0.75V | |
ASIC) | Source CLK | ||
R = 50ohms | |||
| Return CLK# | ||
| Vterm = 0.75V | ||
| Source CLK# | ||
|
| ||
Echo Clock1/Echo Clock#1 |
| ||
Echo Clock2/Echo Clock#2 |
|
R = 250ohms | SRAM#2 |
| ZQ | ||||
|
|
| |||||
|
| DQ | CQ/CQ# | ||||
|
| ||||||
|
| A LD# R/W# C C# | K K# | ||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
R = 250ohms
Document Number: | Page 9 of 30 |
[+] Feedback