Application Example, Programmable Impedance

CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchro- nized to the output clock of the DDR-II. In single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

PLL

These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 μs of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 μs after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time).

Application Example

Figure 1 shows two DDR-II used in an application.

Figure 1. Application Example

SRAM#1 ZQ

DQCQ/CQ#

A LD# R/W# C C# K K#

	DQ
BUS	Addresses
MASTER	Cycle Start#
(CPU	R/W#
or	Return CLK	Vterm = 0.75V
ASIC)	Source CLK	Vterm = 0.75V
ASIC)	Source CLK	R = 50ohms
	Return CLK#	R = 50ohms
	Return CLK#	Vterm = 0.75V
	Source CLK#	Vterm = 0.75V
	Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2

R = 250ohms	SRAM#2		ZQ
	SRAM#2		ZQ
	DQ	CQ/CQ#
	DQ	CQ/CQ#
	A LD# R/W# C C#	K K#

R = 250ohms

Document Number: 001-00437 Rev. *E

Page 9 of 30

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CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, CY7C1518KV18 specifications

The Cypress CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, and CY7C1518KV18 are a series of high-performance asynchronous static random-access memory (SRAM) devices designed for a variety of applications requiring fast data access and reliable operation. These SRAM chips feature density options ranging from 1Mbit to 4Mbit, catering to a broad spectrum of consumer electronics, telecommunications, networking, and industrial applications.

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In summary, the Cypress CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, and CY7C1518KV18 SRAM devices offer high speed, low power consumption, and flexibility in integration. With their advanced technology and robust features, these memory solutions continue to play a vital role in modern electronics, driving innovation across multiple sectors.

Cypress CY7C1516KV18 Application Example, Programmable Impedance, Echo Clocks, SRAM#1 ZQ, SRAM#2

Models: CY7C1516KV18 CY7C1520KV18 CY7C1527KV18 CY7C1518KV18