Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1516KV18, CY7C1520KV18 Pin Configuration continued, Ball FBGA 13 x 15 x 1.4 mm Pinout

Models: CY7C1516KV18 CY7C1520KV18 CY7C1527KV18 CY7C1518KV18

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Pin Configuration (continued)

CY7C1516KV18, CY7C1527KV18

CY7C1518KV18, CY7C1520KV18

Pin Configuration (continued)

The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow. [1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1518KV18 (4M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

CQ

R/W

BWS1

K

NC/144M

LD

A

A

CQ

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

A0

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

C

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1520KV18 (2M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

A

CQ

R/W

BWS2

K

BWS1

LD

A

A

CQ

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

A0

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

C

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document Number: 001-00437 Rev. *E

Page 5 of 30

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Cypress manual Pin Configuration continued, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18

Contents

Configurations FeaturesCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Functional DescriptionLogic Block Diagram CY7C1527KV18 Logic Block Diagram CY7C1516KV18CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 + FeedbackLogic Block Diagram CY7C1520KV18 Logic Block Diagram CY7C1518KV18CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 + FeedbackCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Pin Configuration165-Ball FBGA 13 x 15 x 1.4 mm Pinout 165-Ball FBGA 13 x 15 x 1.4 mm Pinout Pin Configuration continuedCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Pin Definitions CY7C1518KV18, CY7C1520KV18CY7C1516KV18, CY7C1527KV18 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Pin Definitions continued Functional Overview Single Clock ModeRead Operations Write OperationsProgrammable Impedance Application ExampleEcho Clocks CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Truth Table Write Cycle DescriptionsBurst Address Table CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Write Cycle Descriptions CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Write Cycle Descriptions Test Access Port-Test Clock Disabling the JTAG FeatureTest Mode Select TMS Performing a TAP ResetSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSPage 14 of TAP Controller State DiagramCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 TAP Controller Block DiagramTAP Electrical Characteristics CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 TAP AC Switching CharacteristicsTAP Timing and Test Conditions Scan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SRAMPLL Constraints CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeAC Electrical Characteristics Electrical Characteristics continuedDC Electrical Characteristics CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18Thermal Resistance CapacitanceCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 PackageParameter Switching CharacteristicsCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Switching Characteristics continuedCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Switching WaveformsREAD + FeedbackCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Ordering InformationCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 DiagramOrdering Information continued SpeedCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 DiagramOrdering Information continued SpeedCY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Package DiagramFigure 6. 165-Ball FBGA 13 x 15 x 1.4 mm + FeedbackPSoC Solutions Sales, Solutions, and Legal InformationDocument History Page Worldwide Sales and Design Support