Motorola DSP56012 manuals
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Motorola DSP56012 User Manual
270 pages 2.21 Mb
DSP56012 3 Table of Contents13 List of Figures17 List of Tables MOTOROLA DSP56012 Users Manual 1-3 23 1.1 INTRODUCTIONDSP56000 Family Manual DSP56012 Technical Data 1-4 DSP56012 Users Manual MOTOROLA 24 1.1.1 Manual Organization MOTOROLA DSP56012 Users Manual 1-5 25 1.1.2 Manual Conventions 1-6 DSP56012 Users Manual MOTOROLA 26 1.2 DSP56012 FEATURES 27 MOTOROLA DSP56012 Users Manual 1-7 1-8 DSP56012 Users Manual MOTOROLA 28 1.3 DSP56012 ARCHITECTURAL OVERVIEW30 1.3.1 Peripheral Modules1.3.2 DSP Core Processor 33 1.3.3 Memories36 1.3.4 Input/Output43 2.1 SIGNAL GROUPINGS45 2.2 POWERTable 2-2 Power Inputs 2-6 DSP56012 Users Manual MOTOROLA 46 2.3 GROUNDTable 2-3 Grounds Phase Lock Loop (PLL) MOTOROLA DSP56012 Users Manual 2-7 47 2.4 PHASE LOCK LOOP (PLL) Table 2-4 Phase Lock Loop Signals 2-8 DSP56012 Users Manual MOTOROLAInterrupt and Mode Control 48 2.5 INTERRUPT AND MODE CONTROL50 2.6 HOST INTERFACE (HI) 53 2.7 SERIAL HOST INTERFACE (SHI) 56 2.8 SERIAL AUDIO INTERFACE (SAI)The SAI is composed of separate receiver and transmitter sections. 2.8.1 SAI Receive SectionSerial Audio Interface (SAI) MOTOROLA DSP56012 Users Manual 2-17 57 2.8.2 SAI Transmit Section 2-18 DSP56012 Users Manual MOTOROLAGeneral Purpose Input/Output (GPIO) 58 2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) 2.10 DIGITAL AUDIO INTERFACE (DAX) Table 2-10 General Purpose I/O (GPIO) Signals Table 2-11 Digital Audio Interface (DAX) Signals OnCE Port MOTOROLA DSP56012 Users Manual 2-19 59 2.11 OnCE PORTTable 2-12 On-Chip Emulation Port (OnCE) Signals 60 2-20 DSP56012 Users Manual MOTOROLAOnCE Port Table 2-12 On-Chip Emulation Port (OnCE) Signals (Continued) MOTOROLA DSP56012 Users Manual 3-3 63 3.1 INTRODUCTION3.2 DSP56012 DATA AND PROGRAM MEMORY 3-4 DSP56012 Users Manual MOTOROLA 64 3.2.1 X and Y Data ROM3.2.2 Bootstrap ROM 3.3 DSP56012 DATA AND PROGRAM MEMORY MAPS 65 3.3.1 Reserved Memory Spaces 3-8 DSP56012 Users Manual MOTOROLA 68 3.3.2 Dynamic Switch of Memory Configurations70 3.3.3 Internal I/O Memory Map72 3.4 OPERATING MODE REGISTER (OMR)3.4.1 DSP Operating Mode (MC, MB, MA)Bits 4, 1, and 0 3.4.2 Program RAM Enable A and Program RAM Enable B (PEA and PEB)Bits 2 and 3 3.4.3 Stop Delay (SD)Bit 6 MOTOROLA DSP56012 Users Manual 3-13 73 3.5 OPERATING MODES75 3.6 INTERRUPT PRIORITY REGISTER79 3.7 PHASE LOCK LOOP (PLL) CONFIGURATION 3-20 DSP56012 Users Manual MOTOROLA 80 3.8 OPERATION ON HARDWARE RESET MOTOROLA DSP56012 Users Manual 4-3 83 4.1 INTRODUCTION4.2 PORT B CONFIGURATION 86 4.2.1 Port B Control (PBC) Register MOTOROLA DSP56012 Users Manual 4-7 87 4.2.2 Port B Data Direction Register (PBDDR)4.2.3 Port B Data (PBD) Register 4-8 DSP56012 Users Manual MOTOROLA 88 4.3 PROGRAMMING THE GPIO MOTOROLA DSP56012 Users Manual 4-9Figure 4-6 I/O Port B Configuration Note: The Port B GPIO timing differs from the timing of the GPIO peripheral. Please refer to the sheets for the timing specifications. 89 4.4 HOST INTERFACE (HI) 4-10 DSP56012 Users Manual MOTOROLA 90 4.4.1 HI Features MOTOROLA DSP56012 Users Manual 4-11 91 4.4.2 HI Block Diagram 4-12 DSP56012 Users Manual MOTOROLAFigure 4-7 HI Block Diagram 92 4.4.3 HIDSP Viewpoint MOTOROLA DSP56012 Users Manual 4-13 93 4.4.4 Programming ModelDSP Viewpoint101 4.4.5 HI115 4.4.6 HI Signals117 4.4.7 Servicing the HI122 4.4.8 Host Interface Application Examples123 MOTOROLA DSP56012 Users Manual 4-43Figure 4-19 HI InitializationDSP SideX:$FFE8 0 HF3 HF2 HCIE HTIE HRIE X:$FFEC BC 1BC 124 4-44 DSP56012 Users Manual MOTOROLAFigure 4-20 HI InitializationHost Side, Interrupt Mode 125 MOTOROLA DSP56012 Users Manual 4-45126 4-46 DSP56012 Users Manual MOTOROLA127 MOTOROLA DSP56012 Users Manual 4-47AA0332k Figure 4-24 HI InitializationHost Side, DMA Mode SP56012 Technical Data sheet (DSP56012/D).Step 2 Of Host Port configuration 2. Option 5: Select DMA mode for 128 4-48 DSP56012 Users Manual MOTOROLAAA0333 Figure 4-25 Bits Used for Host-to-DSP Transfer 129 MOTOROLA DSP56012 Users Manual 4-49130 4-50 DSP56012 Users Manual MOTOROLAAA0334 Figure 4-26 Data Transfer from Host to DSP 131 MOTOROLA DSP56012 Users Manual 4-51132 4-52 DSP56012 Users Manual MOTOROLAFigure 4-27 Host Command$0052, and $0056. addresses P:$0040$004A, $0050, peripherals, do not use interrupt vector Note: When using the SAI and DAX 133 MOTOROLA DSP56012 Users Manual 4-53134 4-54 DSP56012 Users Manual MOTOROLA135 MOTOROLA DSP56012 Users Manual 4-55Figure 4-31 Bootstrap Using the Host Interface The actual code used in the bootstrap program is provided in Appendix A. 136 4-56 DSP56012 Users Manual MOTOROLA137 MOTOROLA DSP56012 Users Manual 4-57AA0339 Figure 4-32 Bits Used for DSP to Host Transfer 138 4-58 DSP56012 Users Manual MOTOROLAFigure 4-33 Data Transfer from DSP to HostVIEW FROM HOST HTDE HOST TRANSMIT INTERRUPT ENABLE HOST TRANSMIT DATA EMPTY HTIE VIEW FROM HOST 139 MOTOROLA DSP56012 Users Manual 4-59140 4-60 DSP56012 Users Manual MOTOROLAFigure 4-35 HI HardwareDMA Mode1 K AA0341k Characteristics of HI DMA Mode 141 MOTOROLA DSP56012 Users Manual 4-61142 4-62 DSP56012 Users Manual MOTOROLA143 MOTOROLA DSP56012 Users Manual 4-63Figure 4-37 Host to DSP DMA ProcedureHOST PROCESSOR DSP56012DMA CONTROLLER $0052, and $0056. addresses P:$0040$004A, $0050, peripherals, do not use interrupt vector Note: When using the SAI and DAX 144 4-64 DSP56012 Users Manual MOTOROLA145 MOTOROLA DSP56012 Users Manual 4-65146 4-66 DSP56012 Users Manual MOTOROLA147 MOTOROLA DSP56012 Users Manual 4-67 MOTOROLA DSP56012 Users Manual 5-3 151 5.1 INTRODUCTION 5-4 DSP56012 Users Manual MOTOROLA 152 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE MOTOROLA DSP56012 Users Manual 5-5 153 5.3 SHI CLOCK GENERATOR5.4 SERIAL HOST INTERFACE PROGRAMMING MODEL 156 5.4.1 SHI Input/Output Shift Register (IOSR)Host Side5.4.2 SHI Host Transmit Data Register (HTX)DSP Side MOTOROLA DSP56012 Users Manual 5-9 157 5.4.3 SHI Host Receive Data FIFO (HRX)DSP Side5.4.4 SHI Slave Address Register (HSAR)DSP Side 5.4.5 SHI Clock Control Register (HCKR)DSP Side 161 5.4.6 SHI Control/Status Register (HCSR)DSP Side167 5.5 CHARACTERISTICS OF THE SPI BUS 5-20 DSP56012 Users Manual MOTOROLA 168 5.6 CHARACTERISTICS OF THE I2C BUS5.6.1 Overview 170 5.6.2 I2C Data Transfer Formats MOTOROLA DSP56012 Users Manual 5-23 171 5.7 SHI PROGRAMMING CONSIDERATIONS5.7.1 SPI Slave Mode 5-24 DSP56012 Users Manual MOTOROLA 172 5.7.2 SPI Master Mode MOTOROLA DSP56012 Users Manual 5-25 173 5.7.3 I2C Slave Mode175 5.7.4 I2C Master Mode178 5.7.5 SHI Operation During Stop MOTOROLA DSP56012 Users Manual 6-3 181 6.1 INTRODUCTION 6-4 DSP56012 Users Manual MOTOROLA 182 6.2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE6.2.1 Baud-Rate Generator MOTOROLA DSP56012 Users Manual 6-5 183 6.2.2 Receive Section Overview 6-6 DSP56012 Users Manual MOTOROLA 184 6.2.3 SAI Transmit Section Overview185 MOTOROLA DSP56012 Users Manual 6-7 6-8 DSP56012 Users Manual MOTOROLASerial Audio Interface Serial Audio Interface Programming ModelTransmitter 2 Data Register Transmitter 1 Data Register Transmitter 0 Data Register Receiver 1 Data Register Receiver 0 Data Register Figure 6-4 SAI Registers 186 6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODELBaud Rate Control Register (BRC) Receive Control/Status Register (RCS) Transmit Control/Status Register (TCS) read-only read-only X: $FFE2 X: $FFE3 X: $FFE5 X: $FFE6 X: $FFE7X: $FFE0 X: $FFE1 X: $FFE4 MOTOROLA DSP56012 Users Manual 6-9 187 6.3.1 Baud Rate Control Register (BRC) 6-10 DSP56012 Users Manual MOTOROLA 188 6.3.2 Receiver Control/Status Register (RCS)195 6.3.3 SAI Receive Data Registers (RX0 and RX1)6.3.4 Transmitter Control/Status Register (TCS) 201 6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0) 6-24 DSP56012 Users Manual MOTOROLA 202 6.4 PROGRAMMING CONSIDERATIONS6.4.1 SAI Operation During Stop 6.4.2 Initiating a Transmit Session 6.4.3 Using a Single Interrupt to Service Both Receiver and Transmitter Sections MOTOROLA DSP56012 Users Manual 6-25 203 6.4.4 SAI State Machine MOTOROLA DSP56012 Users Manual 7-3 207 7.1 INTRODUCTION7.2 GPIO PROGRAMMING MODEL 7.3 GPIO REGISTER (GPIOR) 7-4 DSP56012 Users Manual MOTOROLA 208 7.3.1 GPIOR Data Bits (GD[7:0])Bits 707.3.2 GPIOR Data Direction Bits (GDD[7:0])Bits 158 7.3.3 GPIOR Control Bits (GC[7:0])Bits 2316 213 8.1 OVERVIEW 8-4 DSP56012 Users Manual MOTOROLA 214 8.2 DAX SIGNALS MOTOROLA DSP56012 Users Manual 8-5 215 8.3 DAX FUNCTIONAL OVERVIEW 8-6 DSP56012 Users Manual MOTOROLA 216 8.4 DAX PROGRAMMING MODEL8.5 DAX INTERNAL ARCHITECTURE MOTOROLA DSP56012 Users Manual 8-7 217 8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB)8.5.2 DAX Audio Data Buffer (XADBUF) 8-8 DSP56012 Users Manual MOTOROLA 218 8.5.3 DAX Audio Data Shift Register (XADSR)8.5.4 DAX Control Register (XCTR) 220 8.5.5 DAX Status Register (XSTR)222 8.5.6 DAX Non-Audio Data Buffer (XNADBUF)8.5.7 DAX Parity Generator (PRTYG) 8.5.8 DAX Biphase Encoder 8.5.9 DAX Preamble Generator MOTOROLA DSP56012 Users Manual 8-13 223 8.5.10 DAX Clock Multiplexer225 8.6.4 DAX Operation During Stop MOTOROLA DSP56012 Users Manual A-1 227 APPENDIXA BOOTSTRAP ROM CONTENTS247 SR Note: The operation and function of the Status Register is detailed in the 248 CENTRAL PROCESSORIRQA Mode Interrupt Priority Register (IPR) DAX IPL IRQB Mode 23 22 21 20 19 18 1617 HI IPL B-16 DSP56012 Users Manual MOTOROLA IPR 250 CENTRAL PROCESSOR0 B-18 DSP56012 Users Manual MOTOROLA PCTL 257 S.H.I. MOTOROLA DSP56012 Users Manual B-25 B-26 DSP56012 Users Manual MOTOROLA 258 S.H.I.0SHI Control/Status X:$FFF1 Reset = $008200 Register (HCSR) SHI Host Control/Status Register (HCSR) MOTOROLA DSP56012 Users Manual B-27Receiver Control/Status X:$FFE1 Reset = $0000 SAI Receiver Control/Status Register (RCS) Register (RCS) 259 * B-28 DSP56012 Users Manual MOTOROLATransmitter Control/ X:$FFE4 Reset = $0000 260 *261 *263 GPIO MOTOROLA DSP56012 Users Manual B-31 265 Index
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