Motorola DSP56012 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE

5-4 DSP56012 User’s Manual MOTOROLA
Serial Host Interface
Serial Host Interface Internal Architecture
5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE
The DSP views the SHI as a memory-mapped peripheral in the X data memory space.
The DSP may use the SHI as a normal memory-mapped peripheral using standard
polling or interrupt programming techniques. Memory mapping allows DSP
communication with the SHI registers to be accomplished using standard
instructions and addressing modes. In addition, the MOVEP instruction allows
interface-to-memory and memory-to-interface data transfers without going through
an intermediate register. The single master configuration allows the DSP to directly
connect to dumb peripheral devices. For that purpose, a programmable baud-rate
generator is included to generate the clock signal for serial transfers. The host side
invokes the SHI, for communication and data transfer with the DSP, through a shift
register that may be accessed serially using either the I2C or the SPI bus protocols.
Figure 5-1 shows the SHI block diagram.
Figure 5-1 Serial Host Interface Block Diagram
DSP
Global
Data
Bus
DSP AccessibleHost Accessible
SCK/SCL
MISO/SDA
MOSI/HA0
SS/HA2
HRX
(FIFO)
HREQ
HCSR
HTX
HCKR
24 BIT
HSAR
Clock
Generator
Controller
Logic
Slave
Address
Recognition
Unit
(SAR)
Pin
Control
Logic INPUT/OUTPUT Shift Register
(IOSR)
AA0416