Motorola xv
Figure 4-36 DMA Transfer and HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .4-61
Figure 4-37 Host to DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .4-63
Figure 5-1 Serial Host Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . .5-4
Figure 5-2 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
Figure 5-3 SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . .5-5
Figure 5-4 SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . . . . . .5-6
Figure 5-5 SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
Figure 5-6 SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . .5-10
Figure 5-7 I
2
C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20
Figure 5-8 I
2
C Start and Stop Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21
Figure 5-9 Acknowledgment on the I
2
C Bus . . . . . . . . . . . . . . . . . . . . . . . .5-21
Figure 5-10 I
2
C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . .5-22
Figure 5-11 I
2
C Bus Protocol For Host Read Cycle. . . . . . . . . . . . . . . . . . . .5-22
Figure 6-1 SAI Baud-Rate Generator Block Diagram . . . . . . . . . . . . . . . . . .6-4
Figure 6-2 SAI Receive Section Block Diagram. . . . . . . . . . . . . . . . . . . . . . .6-5
Figure 6-3 SAI Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . .6-7
Figure 6-4 SAI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
Figure 6-5 Receiver Data Shift Direction (RDIR) Programming. . . . . . . . . .6-12
Figure 6-6 Receiver Left/Right Selection (RLRS) Programming . . . . . . . . .6-12
Figure 6-7 Receiver Clock Polarity (RCKP) Programming. . . . . . . . . . . . . .6-13
Figure 6-8 Receiver Relative Timing (RREL) Programming . . . . . . . . . . . .6-14
Figure 6-9 Receiver Data Word Truncation (RDWT) Programming. . . . . . .6-14
Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming . . . . . . . .6-19