Programming Reference

MOTOROLA DSP56012 User’s Manual B-9

BTST #n,X:<aa> 1+ea 4+mvb - * - - - - - ?
#n,X:<pp>
#n,X:<ea>
#n,Y:<aa>
#n,Y:<pp>
#n,Y:<ea>
#n,D
CLR D (parallel move) 1+mv 2+mv * * ? ? ? ? ? -
CMP S1,S2 (parallel move) 1+mv 2+mv ********
CMPM S1,S2 (parallel move) 1+mv 2+mv ********
DEBUG 1 4 --------
DEBUGcc 1 4 --------
DEC D 1 2 - * * * * * * *
DIV S,D 1 2 - * - - - - ? ?
DO X:<ea>,expr 2 6+mv * * - - - - - -
X:<aa>,expr
Y:<ea>,expr
Y:<aa>,expr
#xxx,expr
S,expr
ENDDO 1 2 --------
EOR S,D (parallel move) 1+mv 2+mv * * - - ? ? 0 -
ILLEGAL 1 8 --------
INC D 1 2 - * * * * * * *
Jcc xxx 1+ea 4+jx --------
JCLR #n,X:<ea>,xxxx 2 6+jx * * - - - - - -
#n,X:<aa>,xxxx
#n,X:<pp>,xxxx
#n,Y:<ea>,xxxx
#n,Y:<aa>,xxxx
#n,Y:<pp>,xxxx

Table B-3 Instruction Set Summary (Sheet 2 of 7)

Mnemonic Syntax Parallel Moves Instruction
Program
Words
Osc.
Clock
Cycles
Status Request
Bits:
SLEUNZVC
- indicates that the bit is unaffected by the operation
* indicates that the bit may be set according to the definition, depending on parallel move conditions
? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of
the
DSP56000 Family Manual
(DSP56KFAMUM/AD)
0 indicates that the bit is cleared