Motorola DSP56012 8.5.10 DAX Clock Multiplexer

Digital Audio Transmitter
DAX Internal Architecture
MOTOROLA DSP56012 User’s Manual 8-13
There is no programmable control for the preamble selection. The first sub-frame to
be transmitted (immediately after the DAX is enabled) is the beginning of a block,
and therefore it has a “Z” preamble. This is followed by the second sub-frame, which
has an “Y” preamble. After that, “X” and “Y” preambles are transmitted alternately
until the end of the block transfer (192 frames transmitted). See Figure 8-4 for an
illustration of the preamble sequence.
8.5.10 DAX Clock Multiplexer
The DAX clock multiplexer selects one of the clock sources and generates the biphase
clock (128 × Fs) and shift clock (64 × Fs). The clock source can be selected from the
following options (see also Section 8.5.4.4 on page 8-9).
• The internal DSP core clock—assumes 1024 × Fs
• DAX clock input pin(ACI)—512 × Fs
• DAX clock input pin(ACI)—384 × Fs
• DAX clock input pin(ACI)—256 × Fs
Figure 8-5 shows how each clock is divided to generate the biphase and bit shift
clocks.
Figure 8-4 Preamble sequence
Figure 8-5 Clock Multiplexer Diagram
DAX
Enabled
Here
First Block (384 Sub-frames) Second Block
ZYXY XYXYZYXY
AA0609k
1/4
2/3
1/2 1/2
1/2
Biphase
Clock
(128 × Fs)
Bit Shift
Clock
(64 × Fs)
DSP Core Clock
(1024 × Fs)
ACI Pin
{256,384,512} × Fs
(XCS1 or XCS0)
XCS0
1
0
XCS1
1
0
1
0
MUX
MUX
MUX
AA0610