Motorola DSP56012 , 1.2 DSP56012 FEATURES

1-6 DSP56012 User’s Manual MOTOROLA
Overview
DSP56012 Features
1.2 DSP56012 FEATURES
• Digital Signal Processing Core
– Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
– 40.5 Million Instructions Per Second (MIPS)—24.69 ns instruction cycle at
81 MHz
– Highly parallel instruction set with unique DSP addressing modes
– Two 56-bit accumulators including extension byte
– Parallel 24 ×
24-bit multiply-accumulate in 1 instruction cycle (2 clock
cycles)
– Double precision 48 ×
48-bit multiply with 96-bit result in 6 instruction
cycles
– 56-bit addition/subtraction in 1 instruction cycle
– Fractional and integer arithmetic with support for multi-precision
arithmetic
– Hardware support for block-floating point Fast Fourier Transforms (FFT)
– Hardware nested DO loops
– Zero-overhead fast interrupts (2 instruction cycles)
Table 1-1 High True / Low True Signal Conventions
Signal/Symbol Logic State Signal State Voltage
PIN
1
True Asserted V
CC3
PIN
1
False Deasserted Ground
2
PIN
1
True Asserted Ground
2
PIN
1
False Deasserted V
CC3
Notes: 1. PIN is a generic term for any pin on the device.
2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range
of acceptable low voltage levels (typically a TTL logic low).
3. V
CC
is an acceptable high voltage level. See the appropriate data sheet for the range of
acceptable high voltage levels (typically a TTL logic high).