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Motorola DSP56012 4-24 DSP56012 Users Manual MOTOROLA

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4-24 DSP56012 User’s Manual MOTOROLA

Parallel Host Interface

Host Interface (HI)

4.4.5.3 Interrupt Control Register (ICR)

The Interrupt Control Register (ICR) is an 8-bit read/write control register used by

the host processor to control the HI interrupts and flags. The ICR cannot be accessed

by the DSP CPU. The ICR is a read/write register that allows the use of bit

manipulation instructions on control register bits. The control bits are described in

the following paragraphs.

4.4.5.3.1 ICR Receive Request Enable (RREQ)—Bit 0

The Receive Request Enable (RREQ) bit is used to control the HOREQ pin for host

receive data transfers. In Interrupt mode (DMA off), RREQ is used to enable

interrupt requests via the external HI Request (HOREQ) pin when the Receive Data

Register Full (RXDF) status bit in the ISR is set. When RREQ is cleared, RXDF

interrupts are disabled. When RREQ is set, the external HOREQ pin will be asserted

if RXDF is set.

In DMA modes, RREQ must be set or cleared by software to select the direction of

DMA transfers. Setting RREQ sets the direction of DMA transfer to be DSP-to-host

and enables the HOREQ pin to request data transfer.

Note: Hardware reset, software reset, individual reset, and Stop clear RREQ.

4.4.5.3.2 ICR Transmit Request Enable (TREQ)—Bit 1

The Transmit Request enable (TREQ) bit is used to control the HOREQ pin for host

transmit data transfers. In Interrupt mode (DMA off), TREQ is used to enable

interrupt requests via the external HOREQ pin when the Transmit Data register

Empty (TXDE) status bit in the ISR is set. When TREQ is cleared, TXDE interrupts are

disabled. When TREQ is set, the external HOREQ pin will be asserted if TXDE is set.

Figure 4-11 HI Register Map

AA0320k

$0

$1

$2

$3

$4

$5

$6

$7

Interrupt Control

Command Vector

Interrupt Status

Interrupt Vector

Unused

Receive/Transmit

Bytes

ICR

CVR

ISR

IVR

0 0 0 0 0 0 0 0

RXH/TXH

RXM/TXM

RXL/TXL

Host Address

HOA[2:0]

HI Data Bus

H[7:0]

Contents

Main DSP56012 Page Table of Contents Page Page Page Page Page Page Page Page Page List of Figures Page Page Page List of Tables Page Page Page Page Page MOTOROLA DSP56012 Users Manual 1-3 1.1 INTRODUCTION DSP56000 Family Manual DSP56012 Technical Data 1.1.1 Manual Organization MOTOROLA DSP56012 Users Manual 1-5 1.1.2 Manual Conventions 1-6 DSP56012 Users Manual MOTOROLA 1.2 DSP56012 FEATURES MOTOROLA DSP56012 Users Manual 1-7 1-8 DSP56012 Users Manual MOTOROLA 1.3 DSP56012 ARCHITECTURAL OVERVIEW Overview DSP56012 Architectural Overview (GPIO) MOTOROLA DSP56012 Users Manual 1-9 Figure 1-1 DSP56012 Block Diagram 1-10 DSP56012 Users Manual MOTOROLA 1.3.1 Peripheral Modules 1.3.2 DSP Core Processor MOTOROLA DSP56012 Users Manual 1-11 1-12 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 1-13 1.3.3 Memories 1-14 DSP56012 Users Manual MOTOROLA Table 1-3 Interrupt Starting Addresses and Sources (Continued) MOTOROLA DSP56012 Users Manual 1-15 1-16 DSP56012 Users Manual MOTOROLA 1.3.4 Input/Output MOTOROLA DSP56012 Users Manual 1-17 Table 1-5 On-chip Peripheral Memory Map 1-18 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 1-19 Page Page Page Signal Groupings MOTOROLA DSP56012 Users Manual 2-3 2.1 SIGNAL GROUPINGS Table 2-1 DSP56012 Functional Signal Groupings 2-4 DSP56012 Users Manual MOTOROLA Signal Groupings Figure 2-1 DSP56012 Signals DSP56012 Power 2.2 POWER Table 2-2 Power Inputs 2-6 DSP56012 Users Manual MOTOROLA Ground 2.3 GROUND Table 2-3 Grounds Phase Lock Loop (PLL) MOTOROLA DSP56012 Users Manual 2-7 2.4 PHASE LOCK LOOP (PLL) Table 2-4 Phase Lock Loop Signals 2-8 DSP56012 Users Manual MOTOROLA Interrupt and Mode Control 2.5 INTERRUPT AND MODE CONTROL Table 2-5 Interrupt and Mode Control Interrupt and Mode Control MOTOROLA DSP56012 Users Manual 2-9 Table 2-5 Interrupt and Mode Control (Continued) 2-10 DSP56012 Users Manual MOTOROLA 2.6 HOST INTERFACE (HI) MOTOROLA DSP56012 Users Manual 2-11 Table 2-6 Host Interface (Continued) 2-12 DSP56012 Users Manual MOTOROLA Table 2-6 Host Interface (Continued) MOTOROLA DSP56012 Users Manual 2-13 2.7 SERIAL HOST INTERFACE (SHI) 2-14 DSP56012 Users Manual MOTOROLA Table 2-7 Serial Host Interface (SHI) Signals (Continued) MOTOROLA DSP56012 Users Manual 2-15 Table 2-7 Serial Host Interface (SHI) Signals (Continued) 2-16 DSP56012 Users Manual MOTOROLA Serial Audio Interface (SAI) 2.8 SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. 2.8.1 SAI Receive Section Serial Audio Interface (SAI) MOTOROLA DSP56012 Users Manual 2-17 2.8.2 SAI Transmit Section 2-18 DSP56012 Users Manual MOTOROLA General Purpose Input/Output (GPIO) 2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) 2.10 DIGITAL AUDIO INTERFACE (DAX) Table 2-10 General Purpose I/O (GPIO) Signals Table 2-11 Digital Audio Interface (DAX) Signals OnCE Port 2.11 OnCE PORT Table 2-12 On-Chip Emulation Port (OnCE) Signals 2-20 DSP56012 Users Manual MOTOROLA OnCE Port Table 2-12 On-Chip Emulation Port (OnCE) Signals (Continued) Page Page MOTOROLA DSP56012 Users Manual 3-3 3.1 INTRODUCTION 3.2 DSP56012 DATA AND PROGRAM MEMORY 3-4 DSP56012 Users Manual MOTOROLA 3.2.1 X and Y Data ROM 3.2.2 Bootstrap ROM 3.3 DSP56012 DATA AND PROGRAM MEMORY MAPS 3.3.1 Reserved Memory Spaces Page Page 3-8 DSP56012 Users Manual MOTOROLA 3.3.2 Dynamic Switch of Memory Configurations MOTOROLA DSP56012 Users Manual 3-9 3-10 DSP56012 Users Manual MOTOROLA 3.3.3 Internal I/O Memory Map MOTOROLA DSP56012 Users Manual 3-11 Table 3-2 Internal I/O Memory Map (Continued) 3-12 DSP56012 Users Manual MOTOROLA 3.4 OPERATING MODE REGISTER (OMR) 3.4.1 DSP Operating Mode (MC, MB, MA)Bits 4, 1, and 0 3.4.2 Program RAM Enable A and Program RAM Enable B (PEA and PEB)Bits 2 and 3 3.4.3 Stop Delay (SD)Bit 6 MOTOROLA DSP56012 Users Manual 3-13 3.5 OPERATING MODES 3-14 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 3-15 3.6 INTERRUPT PRIORITY REGISTER 3-16 DSP56012 Users Manual MOTOROLA Figure 3-6 Interrupt Priority Register (Addr X:$FFFF) Table 3-4 Interrupt Priorities MOTOROLA DSP56012 Users Manual 3-17 Table 3-5 Interrupt Vectors Table 3-4 Interrupt Priorities (Continued) 3-18 DSP56012 Users Manual MOTOROLA Table 3-5 Interrupt Vectors (Continued) MOTOROLA DSP56012 Users Manual 3-19 3.7 PHASE LOCK LOOP (PLL) CONFIGURATION 3-20 DSP56012 Users Manual MOTOROLA 3.8 OPERATION ON HARDWARE RESET Page Page MOTOROLA DSP56012 Users Manual 4-3 4.1 INTRODUCTION 4.2 PORT B CONFIGURATION 4-4 DSP56012 Users Manual MOTOROLA Port B Configuration 11 10 01 MOTOROLA DSP56012 Users Manual 4-5 Figure 4-3 Port B GPIO Signals and Registers 4-6 DSP56012 Users Manual MOTOROLA 4.2.1 Port B Control (PBC) Register MOTOROLA DSP56012 Users Manual 4-7 4.2.2 Port B Data Direction Register (PBDDR) 4.2.3 Port B Data (PBD) Register 4-8 DSP56012 Users Manual MOTOROLA 4.3 PROGRAMMING THE GPIO MOTOROLA DSP56012 Users Manual 4-9 Figure 4-6 I/O Port B Configuration Note: The Port B GPIO timing differs from the timing of the GPIO peripheral. Please refer to the sheets for the timing specifications. 4.4 HOST INTERFACE (HI) 4-10 DSP56012 Users Manual MOTOROLA 4.4.1 HI Features MOTOROLA DSP56012 Users Manual 4-11 4.4.2 HI Block Diagram 4-12 DSP56012 Users Manual MOTOROLA Figure 4-7 HI Block Diagram 4.4.3 HIDSP Viewpoint MOTOROLA DSP56012 Users Manual 4-13 4.4.4 Programming ModelDSP Viewpoint 4-14 DSP56012 Users Manual MOTOROLA Figure 4-8 HI Programming ModelDSP Viewpoint MOTOROLA DSP56012 Users Manual 4-15 4-16 DSP56012 Users Manual MOTOROLA . MOTOROLA DSP56012 Users Manual 4-17 4-18 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-19 4-20 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-21 4.4.5 HI 4-22 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-23 Figure 4-10 Host Processor Programming ModelHost Side 4-24 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-25 4-26 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-27 4-28 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-29 4-30 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-31 4-32 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-33 4-34 DSP56012 Users Manual MOTOROLA Table 4-5 HI Registers after Reset (Host Side) MOTOROLA DSP56012 Users Manual 4-35 4.4.6 HI Signals 4-36 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-37 4.4.7 Servicing the HI 4-38 DSP56012 Users Manual MOTOROLA . DSP56012 Technical Data MOTOROLA DSP56012 Users Manual 4-39 4-40 DSP56012 Users Manual MOTOROLA Figure 4-15 Interrupt Vector Register Read Timing Figure 4-16 HI Interrupt Structure MOTOROLA DSP56012 Users Manual 4-41 4-42 DSP56012 Users Manual MOTOROLA 4.4.8 Host Interface Application Examples MOTOROLA DSP56012 Users Manual 4-43 Figure 4-19 HI InitializationDSP Side X:$FFE8 0 HF3 HF2 HCIE HTIE HRIE 4-44 DSP56012 Users Manual MOTOROLA Figure 4-20 HI InitializationHost Side, Interrupt Mode MOTOROLA DSP56012 Users Manual 4-45 4-46 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-47 AA0332k Figure 4-24 HI InitializationHost Side, DMA Mode SP56012 Technical Data sheet (DSP56012/D) . 4-48 DSP56012 Users Manual MOTOROLA AA0333 Figure 4-25 Bits Used for Host-to-DSP Transfer MOTOROLA DSP56012 Users Manual 4-49 4-50 DSP56012 Users Manual MOTOROLA AA0334 Figure 4-26 Data Transfer from Host to DSP MOTOROLA DSP56012 Users Manual 4-51 4-52 DSP56012 Users Manual MOTOROLA Figure 4-27 Host Command $0052, and $0056. addresses P:$0040$004A, $0050, peripherals, do not use interrupt vector MOTOROLA DSP56012 Users Manual 4-53 4-54 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-55 Figure 4-31 Bootstrap Using the Host Interface The actual code used in the bootstrap program is provided in Appendix A. DSP56012 +5 V 4-56 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-57 AA0339 Figure 4-32 Bits Used for DSP to Host Transfer HOST DSP56012 4-58 DSP56012 Users Manual MOTOROLA Figure 4-33 Data Transfer from DSP to Host VIEW FROM HOST HTDE HOST TRANSMIT INTERRUPT ENABLE MOTOROLA DSP56012 Users Manual 4-59 4-60 DSP56012 Users Manual MOTOROLA Figure 4-35 HI HardwareDMA Mode 1 K AA0341k Characteristics of HI DMA Mode MOTOROLA DSP56012 Users Manual 4-61 4-62 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-63 Figure 4-37 Host to DSP DMA Procedure HOST PROCESSOR DSP56012DMA CONTROLLER $0052, and $0056. 4-64 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-65 4-66 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 4-67 Page Page Page MOTOROLA DSP56012 Users Manual 5-3 5.1 INTRODUCTION 5-4 DSP56012 Users Manual MOTOROLA 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE MOTOROLA DSP56012 Users Manual 5-5 5.3 SHI CLOCK GENERATOR 5.4 SERIAL HOST INTERFACE PROGRAMMING MODEL 5-6 DSP56012 Users Manual MOTOROLA Serial Host Interface Serial Host Interface Programming Model AA0419k Figure 5-4 SHI Programming ModelDSP Side MOTOROLA DSP56012 Users Manual 5-7 5-8 DSP56012 Users Manual MOTOROLA 5.4.1 SHI Input/Output Shift Register (IOSR)Host Side 5.4.2 SHI Host Transmit Data Register (HTX)DSP Side MOTOROLA DSP56012 Users Manual 5-9 5.4.3 SHI Host Receive Data FIFO (HRX)DSP Side 5.4.4 SHI Slave Address Register (HSAR)DSP Side 5.4.5 SHI Clock Control Register (HCKR)DSP Side 5-10 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-11 5-12 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-13 5.4.6 SHI Control/Status Register (HCSR)DSP Side 5-14 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-15 5-16 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-17 5-18 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-19 5.5 CHARACTERISTICS OF THE SPI BUS 5-20 DSP56012 Users Manual MOTOROLA 5.6 CHARACTERISTICS OF THE I2C BUS 5.6.1 Overview MOTOROLA DSP56012 Users Manual 5-21 5-22 DSP56012 Users Manual MOTOROLA 5.6.2 I2C Data Transfer Formats MOTOROLA DSP56012 Users Manual 5-23 5.7 SHI PROGRAMMING CONSIDERATIONS 5.7.1 SPI Slave Mode 5-24 DSP56012 Users Manual MOTOROLA 5.7.2 SPI Master Mode MOTOROLA DSP56012 Users Manual 5-25 5.7.3 I2C Slave Mode 5-26 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-27 5.7.4 I2C Master Mode 5-28 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 5-29 5-30 DSP56012 Users Manual MOTOROLA 5.7.5 SHI Operation During Stop Page Page MOTOROLA DSP56012 Users Manual 6-3 6.1 INTRODUCTION 6-4 DSP56012 Users Manual MOTOROLA 6.2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6.2.1 Baud-Rate Generator MOTOROLA DSP56012 Users Manual 6-5 6.2.2 Receive Section Overview 6-6 DSP56012 Users Manual MOTOROLA 6.2.3 SAI Transmit Section Overview MOTOROLA DSP56012 Users Manual 6-7 6-8 DSP56012 Users Manual MOTOROLA Serial Audio Interface Serial Audio Interface Programming Model Transmitter 2 Data Register Transmitter 1 Data Register 6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL Baud Rate Control Register (BRC) Receive Control/Status Register (RCS) Transmit Control/Status Register (TCS) read-only read-only 6.3.1 Baud Rate Control Register (BRC) 6-10 DSP56012 Users Manual MOTOROLA 6.3.2 Receiver Control/Status Register (RCS) MOTOROLA DSP56012 Users Manual 6-11 6-12 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-13 6-14 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-15 6-16 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-17 6.3.3 SAI Receive Data Registers (RX0 and RX1) 6.3.4 Transmitter Control/Status Register (TCS) 6-18 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-19 6-20 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-21 6-22 DSP56012 Users Manual MOTOROLA MOTOROLA DSP56012 Users Manual 6-23 6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0) 6-24 DSP56012 Users Manual MOTOROLA 6.4 PROGRAMMING CONSIDERATIONS 6.4.1 SAI Operation During Stop 6.4.2 Initiating a Transmit Session 6.4.3 Using a Single Interrupt to Service Both Receiver and Transmitter Sections MOTOROLA DSP56012 Users Manual 6-25 6.4.4 SAI State Machine Page Page Page MOTOROLA DSP56012 Users Manual 7-3 7.1 INTRODUCTION 7.2 GPIO PROGRAMMING MODEL 7.3 GPIO REGISTER (GPIOR) 7-4 DSP56012 Users Manual MOTOROLA 7.3.1 GPIOR Data Bits (GD[7:0])Bits 70 7.3.2 GPIOR Data Direction Bits (GDD[7:0])Bits 158 7.3.3 GPIOR Control Bits (GC[7:0])Bits 2316 MOTOROLA DSP56012 Users Manual 7-5 Page Page Page MOTOROLA DSP56012 Users Manual 8-3 8.1 OVERVIEW 8-4 DSP56012 Users Manual MOTOROLA 8.2 DAX SIGNALS MOTOROLA DSP56012 Users Manual 8-5 8.3 DAX FUNCTIONAL OVERVIEW 8-6 DSP56012 Users Manual MOTOROLA 8.4 DAX PROGRAMMING MODEL 8.5 DAX INTERNAL ARCHITECTURE MOTOROLA DSP56012 Users Manual 8-7 8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB) 8.5.2 DAX Audio Data Buffer (XADBUF) 8-8 DSP56012 Users Manual MOTOROLA 8.5.3 DAX Audio Data Shift Register (XADSR) 8.5.4 DAX Control Register (XCTR) MOTOROLA DSP56012 Users Manual 8-9 8-10 DSP56012 Users Manual MOTOROLA 8.5.5 DAX Status Register (XSTR) MOTOROLA DSP56012 Users Manual 8-11 8-12 DSP56012 Users Manual MOTOROLA 8.5.6 DAX Non-Audio Data Buffer (XNADBUF) 8.5.7 DAX Parity Generator (PRTYG) 8.5.8 DAX Biphase Encoder 8.5.9 DAX Preamble Generator MOTOROLA DSP56012 Users Manual 8-13 8.5.10 DAX Clock Multiplexer Page 8.6.4 DAX Operation During Stop Page MOTOROLA DSP56012 Users Manual A-1 APPENDIXA BOOTSTRAP ROM CONTENTS Page MOTOROLA DSP56012 Users Manual A-3 A.1 INTRODUCTION A.2 BOOTSTRAPPING THE DSP A-4 DSP56012 Users Manual MOTOROLA A.3 BOOTSTRAP PROGRAM LISTING sheet for available Program ROM packages. Note: The internal Program ROM is factory-programmed. Refer to the DSP56012 Technical Data MOTOROLA DSP56012 Users Manual A-5 A-6 DSP56012 Users Manual MOTOROLA Page Page Page B-4 DSP56012 Users Manual MOTOROLA Figure B-1 On-chip Peripheral Memory Map MOTOROLA DSP56012 Users Manual B-5 Table B-1 Interrupt Starting Addresses and Sources B-6 DSP56012 Users Manual MOTOROLA Table B-2 Interrupt Priorities Within an IPL Priority Interrupt Table B-1 Interrupt Starting Addresses and Sources (Continued) MOTOROLA DSP56012 Users Manual B-7 Table B-2 Interrupt Priorities Within an IPL (Continued) Priority Interrupt B-8 DSP56012 Users Manual MOTOROLA Table B-3 Instruction Set Summary (Sheet 1 of 7) MOTOROLA DSP56012 Users Manual B-9 Table B-3 Instruction Set Summary (Sheet 2 of 7) B-10 DSP56012 Users Manual MOTOROLA Table B-3 Instruction Set Summary (Sheet 3 of 7) MOTOROLA DSP56012 Users Manual B-11 Table B-3 Instruction Set Summary (Sheet 4 of 7) B-12 DSP56012 Users Manual MOTOROLA Table B-3 Instruction Set Summary (Sheet 5 of 7) MOTOROLA DSP56012 Users Manual B-13 Table B-3 Instruction Set Summary (Sheet 6 of 7) B-14 DSP56012 Users Manual MOTOROLA Table B-3 Instruction Set Summary (Sheet 7 of 7) MOTOROLA DSP56012 Users Manual B-15 SR Note: The operation and function of the Status Register is detailed in the CENTRAL PROCESSOR IRQA Mode Interrupt Priority Register (IPR) DAX IPL IRQB Mode Page CENTRAL PROCESSOR 0 B-18 DSP56012 Users Manual MOTOROLA PCTL MOTOROLA DSP56012 Users Manual B-19 Port B DSP Side B-20 DSP56012 Users Manual MOTOROLA DSP Side MOTOROLA DSP56012 Users Manual B-21 Processor Side Processor SideHI B-22 DSP56012 Users Manual MOTOROLA Interrupt Status Register (ISR) Interrupt Vector Register (IVR) MOTOROLA DSP56012 Users Manual B-23 Processor Side Page S.H.I. MOTOROLA DSP56012 Users Manual B-25 B-26 DSP56012 Users Manual MOTOROLA 19 18 17 16 23 22 21 20 S.H.I. 0 SHI Control/Status X:$FFF1 Reset = $008200 Register (HCSR) * B-28 DSP56012 Users Manual MOTOROLA Transmitter Control/ X:$FFE4 Reset = $0000 * 0 Status Register (TCS) * 0 MOTOROLA DSP56012 Users Manual B-29 B-30 DSP56012 Users Manual MOTOROLA GPIO MOTOROLA DSP56012 Users Manual B-31 Page Index A B C D H I L M O P R Page T X Y