Motorola DSP56012 4.4.2 HI Block Diagram

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-11
– I/O short addressing provides faster execution with fewer instruction
words.
• Interface—Host side
– Mapping:
• Eight consecutive memory locations
• Memory-mapped peripheral for microprocessors, DMA controllers, etc.
– 8-bit Data Word
– Transfer Modes
• DSP-to-Host
• Host-to-DSP
• Host Command
• Mixed 8-, 16-, and 24-bit data transfers
– Handshaking Protocols
• Software Polled
• Interrupt-Driven and Compatible with MC68000
• Cycle Stealing DMA with Initialization
– Dedicated Interrupts:
• Separate interrupt vectors for each interrupt source
• Special host commands force DSP CPU interrupts under host processor
control, which are useful for:
– Real-time production diagnostics
– Debugging window for program development
– Host control protocols and DMA setup
4.4.2 HI Block Diagram
Figure 4-7 is a block diagram illustrating the registers in the HI. These registers can
be divided vertically down the middle into registers visible to the host processor on
the left and registers visible to the DSP on the right. They can also be divided
horizontally into control (at the top), DSP-to-host data transfer (in the middle), and
host-to-DSP data transfer (at the bottom).