NEC PD78212 manuals
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USER'S MANUAL PD78214 SUB-SERIES8-BIT SINGLE-CHIP MICROCOMPUTER 30 31 278K/II Products 1.1 FEATURES 32 33 1.2 ORDERING INFORMATION AND QUALITY GRADE 1.2.1 Ordering Information34 1.2.2 Quality Grade35 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode(1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window 36 7(2) 68-pin plastic QFJ 37 8(3) 64-pin plastic QFP (14 14 mm) 38 9(4) 74-pin plastic QFP (20 20 mm) 11 40 1.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L)(1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window 41 12(2) 68-pin plastic QFJ 42 13(3) 64-pin plastic QFP (14 14 mm) 43 14(4) 74-pin plastic QFP (20 20 mm) 45 1.4 EXAMPLE APPLICATION SYSTEM (PRINTER)46 1.5 BLOCK DIAGRAM47 1.6 FUNCTIONS49 1.7 DIFFERENCES BETWEEN THE PD78210Note AND PD78213 50 1.8 DIFFERENCES BETWEEN THE PD78218A SUB-SERIES PD78214 SUB-SERIES AND 51 1.9 DIFFERENCES BETWEEN THE PD78212 AND PD78P214(A) PD78P214 AND 1.11 DIFFERENCES BETWEEN THE PD78213(A) AND PD78214, AND THE PD78213 AND PD78212(A) 1.10 DIFFERENCES BETWEEN THE PD78214(A) 52 1.12 DIFFERENCES BETWEEN THE PD78214, AND PD78213, PD78212, PD78P214 1.12.1 Functional Differences 1.12.2 Package Differences 54 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTION LIST 2.1.1 Normal Operating mode(1) Ports 55 26(2) Pins other than those which function as ports 56 2.1.2 PROM Programming Mode (only for the PD78P214, P20/NMI = 12.5 V, RESET = L) 2.2 PIN FUNCTIONS 2.2.1 Normal Operating mode 60 2.2.2 PROM Programming Mode (for the PD78P214) 62 2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING63 34Fig. 2-1 I/O Circuits Provided for Pins 66 CHAPTER 3 CPU FUNCTION 3.1 MEMORY SPACE67 38Fig. 3-1 Memory Map of PD78212 (EA Pin Driven High) 68 39Fig. 3-2 Memory Map of PD78212 (EA Pin Driven Low) 69 40PD78214, or PD78213, Fig. 3-3 Memory Map of PD78P214 (EA Pin Driven Low) 70 41PD78214, Fig. 3-4 Memory Map of PD78P214 (EA Pin Driven High) 71 3.1.1 Internal Program Memory Area3.1.2 Internal RAM Area 72 254 8.1 CONFIGURATION255 226Fig. 8-1 A/D Converter Configuration 257 8.2 A/D CONVERTER MODE REGISTER (ADM)258 229Fig. 8-3 A/D Converter Mode Register (ADM) Format 259 8.3 OPERATION 8.3.1 Basic A/D Converter Operation261 8.3.2 Select Mode262 8.3.3 Scan Mode263 8.3.4 A/D Conversion Activated by Software Start264 8.3.5 A/D Conversion Activated by Hardware Start267 238Fig. 8-12 Scan-Mode A/D Conversion Started by Hardware 268 8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER8.5 SETTING FOR USE OF AN6 AND AN7 8.6 NOTES273 244Fig. 9-1 Asynchronous Serial Interface Configuration 274 9.2 ASYNCHRONOUS SERIAL INTERFACE CONTROL REGISTER275 246Fig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM) 276 9.3 ASYNCHRONOUS SERIAL INTERFACE OPERATIONS 9.3.1 Data Format9.3.2 Parity Types and Operations 277 9.3.3 Transmission278 9.3.4 Reception9.3.5 Reception Error279 250Table 9-1 Causes of Reception Errors Fig. 9-7 Reception Error Timing 280 9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART9.4.2 Baud Rate Generator Control Register (BRGC)281 252Fig. 9-9 Baud Rate Generator Control Register (BRGC) Format 282 9.4.3 Operation of the Baud Rate Generator for UART283 9.5 BAUD RATE SETTING9.5.1 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used284 255Table 9-3 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used 286 257 287 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used9.6 NOTES289 260Fig. 10-1 Block Diagram of the Clock Synchronous Serial Interface 262 291 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM)292 10.3.2 Serial Bus Interface Control Register (SBIC)293 264Fig. 10-3 Format of Serial Bus Interface Control Register (SBIC) 294 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE10.4.1 Basic Operation Timing 296 10.4.2 Operation When Only Transmission Is Permitted10.4.3 Operation When Only Reception Is Permitted 10.4.4 Operation When Both Transmission and Reception Are Permitted 297 10.4.5 Action to Be Taken When the Serial Clock and Shift Become Asynchronous10.5 SBI MODE 10.5.1 Features of SBI 299 10.5.2 Configuration of the Serial Interface300 271Fig. 10-9 Block Diagram of Clock Synchronous Serial Interface 301 10.5.3 Detecting an Address Match10.5.4 Control Registers in SBI Mode302 273Fig. 10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM) 303 274304 275Fig. 10-11 Format of SBIC Register (2/2) 306 10.6 SBI COMMUNICATION AND SIGNALS10.6.1 Bus Release Signal (REL) 307 10.6.2 Command Signal (CMD)10.6.3 Address 308 10.6.4 Command and Data10.6.5 Acknowledge Signal (ACK) 309 10.6.6 Busy Signal (BUSY) and Ready Signal (READY)10.6.7 Signals310 281Fig. 10-23 ACKT Operation (c) When ACKE is set to 0 at the end of transfer Fig. 10-24 ACKE Operations (a) When ACKE is set to 1 at the end of transfer (b) When ACKE is set after transfer has been completed 311 282(d) When ACKE is set to 1 for a short period of time (b) When the ACK signal is output after the ninth pulse of the SCK clock (c) Clear timing when a transfer start is specified in the busy state 312 283Fig. 10-26 BSYE Operation 313 284Table 10-2 Signals in SBI Mode (1/3) 314 285Table 10-2 Signals in SBI Mode (2/3) 315 286Table 10-2 Signals in SBI Mode (3/3) 316 10.6.8 Communication10.6.9 Releasing the Busy State 10.6.10 Setting Wake-Up 10.6.11 Starting Transmission and Reception317 288Fig. 10-27 Sending an Address from Master Device to Slave Device 318 289Fig. 10-28 Sending a Command from Master Device to Slave Device 319 290Fig. 10-29 Sending Data from Master Device to Slave Device 320 291Fig. 10-30 Sending Data from the Slave Device to the Master Device 321 10.7 NOTES322 CHAPTER 11 EDGE DETECTION FUNCTION11.1 EXTERNAL INTERRUPT MODE REGISTERS (INTM0, INTM1)323 294Fig. 11-1 Format of External Interrupt Mode Register 0 (INTM0) 324 295Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1) 296 325 11.2 EDGE DETECTION ON PIN P20s is required to detect the edge. Fig. 11-3 Edge Detection on Pin P20 326 11.3 EDGE DETECTION ON PINS P21 TO P26327 11.4 NOTES330 CHAPTER 12 INTERRUPT FUNCTIONS331 12.1 INTERRUPT REQUEST SOURCES12.1.1 Software Interrupt Request 332 12.1.2 Nonmaskable Interrupt Request12.1.3 Maskable Interrupt Request 12.1.4 Selecting an Interrupt Source 333 12.2 INTERRUPT HANDLING CONTROL REGISTERS305 Table 12-3 Flags for Interrupt Request Sources 334 ) )12.2.1 Interrupt Request Flag Register (IF0) 335 12.2.2 Interrupt Mask Register (MK0)12.2.3 Interrupt Service Mode Register (ISM0) 12.2.4 Priority Specification Flag Register (PR0) 336 12.2.5 Interrupt Status Register (IST)337 12.2.6 Program Status Word (PSW)12.3 INTERRUPT HANDLING 12.3.1 Accepting Software Interrupts 12.3.2 Accepting Nonmaskable Interrupts 340 12.3.3 Accepting Maskable Interrupts341 312Fig. 12-10 Interrupt Handling Algorithm 342 12.3.4 Multiple-Interrupt Handling345 12.3.5 Interrupt Request and Macro Service Pending346 12.3.6 Interrupt and Macro Service Operation Timing348 12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline349 12.4.2 Macro Service Types350 12.4.3 Macro Service Basic Operation351 12.4.4 Macro Service Control Register(1) Macro service control word The macro service function of the 352 12.4.5 Macro Service Type A353 324Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) Table 12-9 Illegal Write Access Conditions and Corresponding Operations 354 325Fig. 12-18 Flow of Data Transfer by Macro Service (Type A) 356 12.4.6 Type B Macro Service357 328Fig. 12-21 Flow of Data Transfer by Macro Service (Type B) 359 330Fig. 12-24 Parallel Data Input Timing 360 12.4.7 Macro Service Type C372 12.5 NOTES375 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM)376 13.1.2 Programmable Wait Control Register (PW)13.2 MEMORY EXPANSION FUNCTION 13.2.1 External Memory Expansion Function348 Fig. 13-3 Read Timing Fig. 13-4 Write Timing 377 13.2.2 1M-Byte Expansion Function378 349Fig. 13-5 Accessing Expansion Data Memory (a) Read cycle (b) Write cycle 379 13.2.3 Memory Mapping with Expanded Memory380 351Fig. 13-6 Data Memory Expansion for PD78212 (When EA = L) 381 352Fig. 13-7 Data Memory Expansion for PD78212 (When EA = H) 382 353PD78213 and Fig. 13-8 Data Memory Expansion for PD78214 (When EA = L) 383 354PD78214 and Fig. 13-9 Data Memory Expansion for PD78P214 (When EA = H) 384 13.2.4 Example of Connecting Memories385 356Fig. 13-10 Example of Connecting Memories to PD78214 386 13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION13.4 WAIT FUNCTION387 358Fig. 13-11 Wait Control Space of PD78212 (When EA = L) 388 359Fig. 13-12 Wait Control Space of PD78212 (When EA = H) 389 360PD78213 and Fig. 13-13 Wait Control Space of PD78214 (When EA = L) 390 361PD78214 and Fig. 13-14 Wait Control Space of PD78P214 391 362Fig. 13-15 Read Timing of Programmable Wait Function (1/2) (a) When zero wait states are set (b) When one wait state is set 392 363Fig. 13-15 Read Timing of Programmable Wait Function (2/2) (c) When two wait states are set 393 364Fig. 13-16 Write Timing of Programmable Wait Function (1/2) (a) When zero wait states are set (b) When one wait state is set 394 365Fig. 13-16 Write Timing of Programmable Wait Function (2/2) (c) When two wait states are set 395 366Fig. 13-17 Timing When External Wait Signal Is Used (a) Read timing (b) Write timing 396 13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function13.5.2 Refresh Mode Register (RFM) 397 13.5.3 Operation400 371Fig. 13-22 Return from Self-Refresh 401 13.5.4 Example of Connecting Pseudo Static RAM13.6 NOTES404 375Fig. 13-27 Preventing Problems That May Occur during Emulation 406 CHAPTER 14 STANDBY FUNCTION 14.1 FUNCTION OVERVIEW407 378Fig. 14-2 Standby Function Block 379 408 14.2 STANDBY CONTROL REGISTER (STBC)14.3 HALT MODE 14.3.1 Specifying HALT Mode and Operation States in HALT ModeTable 14-1 Operation States in HALT Mode 380 409 14.3.2 Releasing HALT Mode411 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode14.4.2 Releasing STOP Mode 413 14.4.3 Notes on Using STOP Mode415 14.5 NOTES416 387Fig. 14-9 Example of Longer Oscillation Settling Time 418 CHAPTER 15 RESET FUNCTION 15.1 RESET FUNCTION419 390Table 15-1 Pin States during Reset and After Reset State Is Released 391 420 Chapter 15 Reset FunctionTable 15-2 Hardware States after Reset (1/2) 421 392Table 15-2 Hardware States after Reset (2/2) 422 Chapter 15 Reset Function15.2 NOTE 424 16CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS425 396Fig. 16-1 Example of Controlling Two Stepper Motors 426 Chapter 16 Application Examples16 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES427 398Fig. 16-3 Example of Communication with SBI Fig. 16-4 Serial Bus Communication Timing 428 17CHAPTER 17 PROGRAMMING FOR THE PD78P214 17.1 OPERATING MODE 17.2 PROCEDURE FOR WRITING INTO PROM429 400Fig. 17-1 Timing Chart for PROM Write and Verify 430 Chapter 17 Programming for The PD7821417 17.3 PROCEDURE FOR READING FROM PROM 431 17.4 NOTE432 CHAPTER 18 INSTRUCTION OPERATIONS18.1 LEGEND 18.1.1 Operand Field 433 18.1.2 Operation Field434 18.1.3 Flag Field435 18.2 LIST OF OPERATIONS(1) 8-bit data transfer instructions: MOV, XCH 436 407(2) 16-bit data transfer instructions: MOVW (3) 8-bit arithmetic/logical instructions: ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP 438 409(4) 16-bit arithmetic/logical instructions: ADDW, SUBW, CMPW 439 410(5) Multiply/divide instructions: MULU, DIVUW (7) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4 (6) Increment/decrement instructions: INC, DEC, INCW, DECW 440 411(8) BCD conversion instructions: ADJBA, ADJBS (9) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1 442 413(10) Call/return instructions: CALL, CALLF, CALLT, BRK, RET, RETI, RETB (12) Unconditional branch instruction: BR (11) Stack manipulation instructions: PUSH, POP, MOVW, INCW, DECW 443 414(13) Conditional branch instructions: BC, BL, BNC, BNL, BZ, BE, BNZ, BNE, BT, BF, BTCLR, DBNZ 444 415(14) CPU control instructions: MOV, SEL, NOP, EI, DI 416 445 18.3 INSTRUCTION LISTS FOR EACH ADDRESSING TYPE446 417447 418459 430it is used as a stand-alone emulator. When the in-circuit emulator is connected to the console so that When the in-circuit emulator is connected to the host mahine DEVELOPMENT ENVIRONMENT 460 B.1 HARDWARE (1/2)461 HARDWARE (2/2)462 B.2 SOFTWARE B.2.1 Language Processing Software (1/3)463 Language Processing Software (2/3)464 Language Processing Software (3/3)B.2.2 Software for the In-Circuit Emulator (1/2) Software for the In-Circuit Emulator (2/2) 465 ()
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