NEC PD78212, PD78213, PD78214, PD78P214 1.8 DIFFERENCES BETWEEN THE , PD78218A SUB-SERIES, PD78214 SUB-SERIES AND

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Chapter 1 General
1
Series name µ PD78214 Sub-Series µ PD78218A Sub-Series
µ PD78214
µ PD78214(A)
µ PD78218A
Product
µ PD78212
µ PD78212(A)
µ PD78213
µ PD78213(A)
µ PD78P214
µ PD78P214(A)
µ PD78217A µ PD78P218A
Minimum instruction cycle
(when operating at 12 MHz) 333 ns 500 ns 333 ns 333 ns500 ns
Operating voltage range
ROM
RAM
ROM-less 16K bytes
(masked ROM)
ROM-less
Internal memory 8K bytes
(masked ROM)
16K bytes
(PROM)
32K bytes
(masked ROM)
32K bytes
(PROM)
VDD = +5 V ±10%
512 bytes 1024 bytes384 bytes
Number of I/O pins 54 36 54 5436
Execution time (number of
clocks) required for PUSH
PSW instruction
•Five or seven when internal dual-port RAM is
used for the stack area
•Seven or nine in all other cases
•Six when internal dual-port RAM
is used for the stack area
•Eight in all other cases
One-shot output of 16-bit
timer/counter
Bit width of macro-service
counter
MPD or MPT increment in
macro-service type C
Restriction imposed on data
transfer from memory to SFR
in macro-service type A
Macro-service execution time
None Supported
Eight bits Eight bits or 16 bits (selectable,
except for macro service type A)
Only the eight lower-order bits are incremented.
(The eight high-order bits remain as is.) The 16 bits are incremented.
Transfer data shall not be D0H to DFH.
Transfer source buffer (memory)
addresses shall not be 0FED0H to
0FEDFH.
The macro-service execution time depends on the macro-service mode and other
factors, and also varies with the sub-series. For details, refer to the table of macro-
service execution times in the relevant user's manual.
Restriction imposed
on input voltage
Restriction imposed
on the AVREF voltage
A voltage ranging from 0 V to AVREF can be
applied only to those pins for which A/D conver-
sion is performed and the pins selected by the
ANI0 to ANI3 bits of the ADM register.
A voltage ranging from 0 V to
AVREF can be applied only to those
pins for which A/D conversion is
being performed.
A/D converter
3.4 V to VDD 3.6 V to VDD
Oscillation settling time when
STOP mode is released
Pulse width of NMI at its active level, plus 16
counts on the corresponding counter
15 counts on the corresponding
counter or pulse width of NMI at its
active level, plus 16 counts on the
corresponding counter
•64-pin plastic shrink DIP (750 mil) for all
products
•64-pin plastic QUIP for all products other than
µ PD78212, µ PD78212(A), and µ PD78P214(A)
•68-pin plastic QFJ for all products other than
µ PD78212, µ PD78212(A), µ PD78213(A), and
µ PD78P214(A)
•64-pin plastic QFP (14 × 14 mm) for all products
other than µ PD78213(A)
•74-pin plastic QFP (20 × 20 mm) for all products
other than µ PD78212(A), µ PD78213(A), and
µ PD78P214(A)
•64-pin ceramic shrink DIP with window (750
mil) for µ PD78P214 only
•64-pin plastic shrink DIP (750 mil)
for all products
•64-pin plastic QFP (14 × 14 mm)
for all products
•64-pin ceramic shrink DIP with
window (750 mil) for the
µ PD78P218A only
Package
VDD = +5 V
±0.3 V
1.8 DIFFERENCES BETWEEN THE µ PD78214 SUB-SERIES AND µ PD78218A SUB-SERIES