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Chapter 13 Local Bus Interface Function
13
Fig. 13-15 Read Timing of Programmable Wait Function (2/2)(c) When two wait states are set
Higher address
Lower
address
(output)
Data (input)
Hi-Z Hi-Z
A8-A15
(output)
AD0-AD7
ASTB (output)
RD (output)
fCLKNote
Note fCLK: System clock frequency (fXX/2)