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Contents
8-9 Software-Started Scan-Mode A/D Conversion.......................................................................... 235
8-10 Example of Malfunction in a Hardware-Started A/D Conversion........................................... 236
8-11 Select-Mode A/D Conversion Started by Hardware .................................................................237
8-12 Scan-Mode A/D Conversion Started by Hardware ...................................................................238
8-13 Example of Capacitors Connected to the A/D Converter Pins ................................................240
8-14 Example of Malfunction in a Hardware-Started A/D Conversion........................................... 241
9-1 Asynchronous Serial Interface Configuration ...........................................................................244
9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM)....................................246
9-3 Format of the Asynchronous Serial Interface Status Register (ASIS) ...................................247
9-4 Format of the Transmission/Reception Data at the Asynchronous Serial Interface............ 247
9-5 Asynchronous Serial Interface Transmission Completion Interrupt Timing ........................248
9-6 Asynchronous Serial Interface Reception Completion Interrupt Timing...............................249
9-7 Reception Error Timing ................................................................................................................250
9-8 Baud Rate Generator Clock Configuration.................................................................................25 1
9-9 Baud Rate Generator Control Register (BRGC) Format ...........................................................252
10-1 Block Diagram of the Clock Synchronous Serial Interface...................................................... 260
10-2 Format of the Clock Synchronous Serial Interface Mode Register (CSIM) ...........................262
10-3 Format of Serial Bus Interface Control Register (SBIC) ...........................................................264
10-4 Sample System Configuration with Three-Wire Serial I/O...................................................... 265
10-5 Timing in Three-Wire Serial I/O Mode .......................................................................................266
10-6 Sample Connection with a Device Having Two-Wire Serial I/O .............................................266
10-7 Sample Serial Bus Configured with SBI.....................................................................................269
10-8 Pin Configuration...........................................................................................................................270
10-9 Block Diagram of Clock Synchronous Serial Interface.............................................................271
10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM).................................. 273
10-11 Format of SBIC Register............................................................................................................... 274
10-12 Configuration of Shift Register and Related Components ......................................................276
10-13 SBI Transfer Timing ......................................................................................................................277
10-14 Bus Release Signal........................................................................................................................2 77
10-15 Command Signal........................................................................................................................... 278
10-16 Address........................................................................................................................................... 278
10-17 Selecting a Slave Device by Its Address.................................................................................... 278
10-18 Command .......................................................................................................................................279
10-19 Data .................................................................................................................................................279
10-20 Acknowledge Signal .....................................................................................................................279
10-21 Busy Signal and Ready Signal ....................................................................................................280
10-22 Operation of RELT, CMDT, RELD, and CMDD ...........................................................................280
10-23 ACKT Operation............................................................................................................................. 281
10-24 ACKE Operations........................................................................................................................... 281
10-25 ACKD Operations...........................................................................................................................282
10-26 BSYE Operation .............................................................................................................................283
10-27 Sending an Address from Master Device to Slave Device...................................................... 288
10-28 Sending a Command from Master Device to Slave Device ....................................................289
10-29 Sending Data from Master Device to Slave Device..................................................................290
10-30 Sending Data from the Slave Device to the Master Device ....................................................291
Fig. No. Title, Page