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NEC PD78212, PD78213, PD78214, PD78P214 12.2.5 Interrupt Status Register (IST)

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Chapter 12 Interrupt Functions

12

When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higher

priorities are accepted for multiple-interrupt handling provided that interrupts are enabled. When a high-priority

interrupt is being handled, high-priority vectored interrupts are accepted for multiple-interrupt handling provided

that interrupts are enabled. Moreover, any interrupt requests specifying a macro service are accepted regardless

of their priority.

When the RESET signal is input, this register is set to FFFFH, thereby specifying that all interrupts be in the low-

priority group.

Fig. 12-6 Priority Specification Flag Register (PR0) Format

12.2.5 Interrupt Status Register (IST)

The IST register is an 8-bit register that controls multiple-interrupt handling for nonmaskable interrupt requests

(input to the NMI pin) and indicates whether a nonmaskable interrupt request has been accepted.

When a nonmaskable interrupt is being handled, another nonmaskable interrupt request may occur. In such a

case, the nonmaskable interrupt request is accepted if the NMIS bit is 0; it is not accepted if the NMIS bit is 1.

The NMIS bit is set to 1 when a nonmaskable interrupt request is accepted. It is reset to 0, when a return (execution

of the RETI instruction) from the interrupt handling for the nonmaskable interrupt request occurs.

Both an 8-bit manipulation instruction and bit manipulation instruction can be used to read data from and write

data to the IST register. The NMIS flag is set to 1 when a nonmaskable interrupt is accepted. It is reset to 0 by the

RETI instruction. Fig. 12-7 shows the format of the IST register.

When the RESET signal is input, the register is reset to 00H.

Fig. 12-7 Interrupt Status Register (IST) Format

Multiple interrupt processing by

nonmaskable interrupt request

NMIS

Enabled

Execution exits from nonmaskable

interrupt processing or nonmaskable

interrupt request is not accepted.

0

Disabled Nonmaskable interrupt request is

accepted or being processed.

1

0

7

0

6

0

5

0

4

0

3

0

2

0

1

NMIS

0

IST

Accepting status for

nonmaskable interrupt request

CSIPR STPR SR

PR SERPR

CPR20

PPR5 PPR4

CPR21

PR0H

High priority0

Low priority1

CPR11 CPR10 CPR01 CPR00

PPR3 PPR2 PPR1 PPR0PR0L (FFFFH when RESET signal is input)

Priority specification flags

76543210

Contents

Main USER'S MANUAL PD78214 SUB-SERIES 8-BIT SINGLE-CHIP MICROCOMPUTER Page Page Page Main Revisions in This Edition Major changes in this revision are indicated by stars () in the margins. PREFACE Users: Purpose: Organization: Guidance: Notation: PD78214 sub-series Serial Bus Interface (SBI) Users Manual (IEM-1303) Documents related to development tools Documents related to software to be incorporated into the product Other documents Page CONTENTS Page ContentsPreface Page Page Page Page LIST OF FIGURES Page Page Page Page Page Page Page Page LIST OF TABLES Page CHAPTER 1 GENERAL 2 78K/II Products 1.1 FEATURES 1.2 ORDERING INFORMATION AND QUALITY GRADE 1.2.1 Ordering Information 1.2.2 Quality Grade 6 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window 7 (2) 68-pin plastic QFJ 8 (3) 64-pin plastic QFP (14 14 mm) 9 (4) 74-pin plastic QFP (20 20 mm) Page 11 1.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L) (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window 12 (2) 68-pin plastic QFJ 13 (3) 64-pin plastic QFP (14 14 mm) 14 (4) 74-pin plastic QFP (20 20 mm) Page 1.4 EXAMPLE APPLICATION SYSTEM (PRINTER) 1.5 BLOCK DIAGRAM 1.6 FUNCTIONS Page 1.7 DIFFERENCES BETWEEN THE PD78210Note AND PD78213 1.8 DIFFERENCES BETWEEN THE PD78218A SUB-SERIES PD78214 SUB-SERIES AND 1.9 DIFFERENCES BETWEEN THE PD78212 AND PD78P214(A) PD78P214 AND 1.11 DIFFERENCES BETWEEN THE 1.12 DIFFERENCES BETWEEN THE PD78214, AND PD78213, PD78212, 23 Page 25 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTION LIST 2.1.1 Normal Operating mode (1) Ports 26 (2) Pins other than those which function as ports 2.1.2 PROM Programming Mode (only for the PD78P214, P20/NMI = 12.5 V, RESET = L) 2.2 PIN FUNCTIONS 2.2.1 Normal Operating mode Page Page Page 2.2.2 PROM Programming Mode (for the PD78P214) Page 33 2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING 34 Fig. 2-1 I/O Circuits Provided for Pins Page Page CHAPTER 3 CPU FUNCTION 3.1 MEMORY SPACE 38 Fig. 3-1 Memory Map of PD78212 (EA Pin Driven High) 39 Fig. 3-2 Memory Map of PD78212 (EA Pin Driven Low) 40 PD78214, or PD78213, Fig. 3-3 Memory Map of PD78P214 (EA Pin Driven Low) 41 PD78214, Fig. 3-4 Memory Map of PD78P214 (EA Pin Driven High) 3.1.1 Internal Program Memory Area 3.1.2 Internal RAM Area 3.1.3 Special Function Register (SFR) Area 3.1.4 External SFR Area 3.1.5 External Memory Space Page 3.2 REGISTERS 3.2.1 Program Counter (PC) 3.2.2 Program Status Word (PSW) 3.2.3 Stack Pointer (SP) 47 Fig. 3-9 Data Saved to the Stack Area Fig. 3-10 Data Restored from the Stack Area 3.2.4 General-Purpose Registers 48 Fig. 3-11 Configuration of General-Purpose Registers Page 3.2.5 Special Function Registers (SFR) 51 Table 3-4 Special Function Registers (SFR) (1/2) Page 3.3 NOTES Page 4 CHAPTER 4 CLOCK GENERATOR 4.1 CONFIGURATION AND FUNCTION 4.2 NOTES 4.2.1 Inputting an External Clock 4.2.2 Using the Crystal/Ceramic Oscillator Chapter 4 Clock Generator Page 59 CHAPTER 5 PORT FUNCTIONS 5.1 DIGITAL I/O PORTS The 60 Table 5-1 Port Functions Table 5-2 Number of I/O Ports 5.2 PORT 0 61 5.2.1 Hardware Configuration Fig. 5-2 shows the hardware configuration of port 0. Fig. 5-2 Configuration of Port 0 5.2.2 Setting the Input/Output Mode and Control Mode 5.2.3 Operation 5.2.4 Built-In Pull-Up Resistor 5.2.5 Driving Transistors 5.3 PORT 2 5.3.1 Hardware Configuration 5.3.2 Setting the Input Mode and Control Mode 5.3.3 Operation 5.3.4 Built-In Pull-Up Resistor 5.4 PORT 3 Page 68 5.4.1 Hardware Configuration Fig. 5-10 through 5-13 show the configuration of port 3. Fig. 5-10 Block Diagram of P30 (Port 3) 69 Fig. 5-11 Block Diagram of P31, and P34 through P37 (Port 3) 70 Fig. 5-12 Block Diagram of P32 (Port 3) 71 Fig. 5-13 Block Diagram of P33 (Port 3) 5.4.2 Setting the I/O Mode and Control Mode 72 Fig. 5-14 Port 3 Mode Register Format Fig. 5-15 Port 3 Mode Control Register (PMC3) Format 5.4.3 Operation 5.4.4 Built-In Pull-Up Resistor 5.5 PORT 4 76 5.5.1 Hardware Configuration PD78213, port 4 functions only as the address/data bus (AD0 through AD7). For the Fig. 5-21 shows the hardware configuration of port 4. Fig. 5-21 Block Diagram of Port 4 5.5.2 Setting the I/O Mode and Control Mode 5.5.3 Operation 5.5.4 Built-In Pull-Up Resistor 5.5.5 Driving LEDs Directly 5.6 PORT 5 5.6.1 Hardware Configuration 5.6.2 Setting the I/O Mode and Control Mode 5.6.3 Operation 82 Fig. 5-30 Port Specified as an Input Port 5.6.4 Built-In Pull-Up Resistor 83 Fig. 5-32 Connection of Pull-Up Resistors (Port 5) 5.6.5 Driving LEDs Directly 5.7 PORT 6 5.7.1 Hardware Configuration 86 Fig. 5-35 Block Diagram of P64 and P65 (Port 6) 87 Fig. 5-36 Block Diagram of P66 (Port 6) 88 Fig. 5-37 Block Diagram of P67 (Port 6) 5.7.2 Setting the I/O Mode and Control Mode 89 Fig. 5-38 Port 6 Mode Register Format 5.7.3 Operation 5.7.4 Built-In Pull-Up Resistor 5.7.5 Note 5.8 PORT 7 5.8.1 Hardware Configuration 5.8.2 Setting the I/O Mode and Control Mode 5.8.3 Operation 5.8.4 Built-In Pull-Up Resistor 5.8.5 Notes 5.9 NOTES Page Page 96 Fig. 6-1 Block Diagram of the Real-Time Output Port 97 6.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) 6.3 ACCESS TO THE REAL-TIME OUTPUT PORT 98 Table 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers 6.4 OPERATION 100 Fig. 6-4 Real-Time Output Port Operation Timing 101 6.5 APPLICATION EXAMPLE 103 Fig. 6-7 Contents of the Control Register for the Real-Time Output Function Fig. 6-8 Real-Time Output Function Setting Procedure 6.6 NOTES Page Page 107 CHAPTER 7 TIMER/COUNTER UNITS The 108 Fig. 7-1 Block Diagrams of Timer/Counter Units 16-bit timer/counter unit 8-bit timer/counter unit 1 8-bit timer/counter unit 2 7.1 16-BIT TIMER/COUNTER 7.1.1 Functions 7.1.2 Configuration 110 Fig. 7-2 Block Diagram of 16-Bit Timer/Counter 7.1.3 16-Bit Timer/Counter Control Registers 112 Fig. 7-3 Format of Timer Control Register 0 (TMC0) Page 7.1.4 Operation of 16-Bit Timer 0 (TM0) Page Page 7.1.5 Compare Register and Capture Register Operations Page 7.1.6 Basic Operation of Output Control Circuit 120 Table 7-5 Timer Output (TO0, TO1) Operation Page 7.1.7 PWM Output 123 Fig. 7-14 Example of PWM Output Using TM0 Fig. 7-15 PWM Output When CR00 = FFFFH 124 Fig. 7-17 Example of PWM Output Signal with a 100% Duty Factor 7.1.8 PPG Output 126 Fig. 7-19 PPG Output When CR00 = CR01 Fig. 7-20 PPG Output When CR00 = 0000H 127 Fig. 7-22 Example of PPG Output Signal with a 100% Duty Factor 128 Fig. 7-23 Example of PPG Output Period Made Longer 7.1.9 Sample Applications Page Page Page 133 Fig. 7-31 Timing of Pulse Width Measurement (b) Capture/compare control register 0 (CRC0) 134 (c) External interrupt mode register 1 (INTM1) Fig. 7-34 Interrupt Request Handling for Pulse Width Calculation Fig. 7-33 Setting Procedure for Pulse Width Measurement Page 136 Fig. 7-37 Setting Procedure for PWM Output Fig. 7-38 Changing Duty Factor of PWM Output Page 138 Fig. 7-41 Setting Procedure for PPG Output Fig. 7-42 Changing Duty Factor of PPG Output 139 7.2 8-BIT TIMER/COUNTER 1 7.2.1 Functions Page 141 Fig. 7-43 Block Diagram of 8-Bit Timer/Counter 1 Page 7.2.3 8-Bit Timer/Counter 1 Control Registers 144 Fig. 7-45 Format of Prescaler Mode Register 1 (PRM1) 7.2.4 Operation of 8-Bit Timer 1 (TM1) Page Page 7.2.5 Compare Register and Capture/Compare Register Operations Page 150 Fig. 7-53 Capture Operation 7.2.6 Sample Applications 152 Fig. 7-55 Timing of Interval Timer Operation (1) Fig. 7-56 Setting of Control Registers for Interval Timer Operation (1) Page 154 Fig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register) Fig. 7-60 Setting of Control Registers for Interval Timer Operation (2) Page 156 Fig. 7-62 Timing of Pulse Width Measurement (When CR11 Is Used As a Capture Register) 157 Fig. 7-63 Setting of Control Registers for Pulse Width Measurement (d) External interrupt mode register 0 (INTM0) 158 Fig. 7-64 Setting Procedure for Pulse Width Measurement Fig. 7-65 Interrupt Request Handling for Pulse Width Calculation 159 7.3 8-BIT TIMER/COUNTER 2 7.3.1 Functions 160 7.3.2 Configuration 162 Fig. 7-66 Block Diagram of 8-Bit Timer/Counter 2 7.3.3 8-Bit Timer/Counter 2 Control Registers 164 165 Page 7.3.4 Operation of 8-Bit Timer 2 (TM2) Page Page 7.3.5 External Event Counter Function 171 (2) When occurrences of both edges are counted (maximum frequency = fCLK/32) Page Page 174 (b) Count value read processing 7.3.6 One-Shot Timer Function 7.3.7 Compare Register and Capture Register Operations Page 178 Fig. 7-82 Capture Operation 7.3.8 Basic Operation of Output Control Circuit 180 Table 7-15 Timer Output (TO2, TO3) Operation Page 182 Table 7-16 TO2 and TO3 Toggle Output (fCLK = 6 MHz) Fig. 7-85 PWM Pulse Output 7.3.9 PWM Output 183 Table 7-17 PWM Output on TO2 and TO3 (fCLK = 6 MHz) 184 Fig. 7-87 PWM Output When CR20 = FFH 7.3.10 PPG Output 186 Table 7-18 PPG Output on TO2 (fCLK = 6 MHz) 187 Fig. 7-91 PPG Output When CR20 = CR21 Fig. 7-92 PPG Output When CR20 = 00H 188 Fig. 7-94 Example of PPG Output Signal with a 100% Duty Factor 189 Fig. 7-95 Example of PPG Output Period Made Longer 7.3.11 Sample Applications 191 Fig. 7-97 Setting of Control Registers for Interval Timer Operation (1) (b) Capture /compare control register 0 (CRC0) Fig. 7-98 Setting Procedure for Interval Timer Operation (1) Page 193 Fig. 7-101 Setting of Control Registers for Interval Timer Operation (2) (b) Capture/compare control register 2 (CRC2) Page 195 Fig. 7-103 Timing of Pulse Width Measurement Fig. 7-104 Setting of Control Registers for Pulse Width Measurement (b) Capture/compare control register 2 (CRC2) 196 (d) External interrupt mode register 0 (INTM0) Fig. 7-105 Setting Procedure for Pulse Width Measurement Page 198 Fig. 7-108 Setting of Control Registers for PWM Output Operation (e) Port 3 mode control register (PMC3) (c) Capture/compare control register 2 (CRC2) (d) Timer output control register (TOC) Page 200 Fig. 7-112 Setting of Control Registers for PPG Output Operation (e) Port 3 mode control register (PMC3) (c) Capture/compare control register 2 (CRC2) (d) Timer output control register (TOC) Page Page Page 204 Fig. 7-120 Setting Procedure for One-Shot Timer Operation Fig. 7-121 Procedure for Starting an Additional One-Shot Timer Operation 205 7.4 8-BIT TIMER/COUNTER 3 7.4.1 Functions 7.4.2 Configuration Page 7.4.3 8-Bit Timer/Counter 3 Control Registers 7.4.4 Operation of 8-Bit Timer 3 (TM3) Page 7.4.5 Compare Register Operation 7.4.6 Sample Applications 7.5 NOTES 7.5.1 Common Notes on All Timers/Counters Page Page Page Page Page Page 7.5.2 Notes on 16-Bit Timer/Counter 7.5.3 Notes on 8-Bit Timer/Counter 2 Page 221 (b) Count value read processing 7.5.4 Notes on Using In-Circuit Emulators 223 Fig. 7-141 Interrupt Generation Timing Change by an Erroneously Detected Edge Page CHAPTER 8 A/D CONVERTER 8.1 CONFIGURATION 226 Fig. 8-1 A/D Converter Configuration Page 8.2 A/D CONVERTER MODE REGISTER (ADM) 229 Fig. 8-3 A/D Converter Mode Register (ADM) Format 8.3 OPERATION 8.3.1 Basic A/D Converter Operation Page 232 8.3.2 Select Mode (b) TRG bit 1 233 8.3.3 Scan Mode (b) TRG bit 1 8.3.4 A/D Conversion Activated by Software Start 8.3.5 A/D Conversion Activated by Hardware Start Page Page 238 Fig. 8-12 Scan-Mode A/D Conversion Started by Hardware 8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER 8.5 SETTING FOR USE OF AN6 AND AN7 8.6 NOTES Page Page Page Page 244 Fig. 9-1 Asynchronous Serial Interface Configuration 9.2 ASYNCHRONOUS SERIAL INTERFACE CONTROL REGISTER 246 Fig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM) 9.3 ASYNCHRONOUS SERIAL INTERFACE OPERATIONS 9.3.1 Data Format 9.3.2 Parity Types and Operations 9.3.3 Transmission 9.3.4 Reception 9.3.5 Reception Error 250 Table 9-1 Causes of Reception Errors Fig. 9-7 Reception Error Timing 9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART 9.4.2 Baud Rate Generator Control Register (BRGC) 252 Fig. 9-9 Baud Rate Generator Control Register (BRGC) Format 9.4.3 Operation of the Baud Rate Generator for UART 254 9.5 BAUD RATE SETTING 9.5.1 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used 255 Table 9-3 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used Page 257 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used 9.6 NOTES Page 260 Fig. 10-1 Block Diagram of the Clock Synchronous Serial Interface Selector Page 262 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM) 10.3.2 Serial Bus Interface Control Register (SBIC) 264 Fig. 10-3 Format of Serial Bus Interface Control Register (SBIC) 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE 10.4.1 Basic Operation Timing Page 10.4.2 Operation When Only Transmission Is Permitted 10.4.3 Operation When Only Reception Is Permitted 10.4.4 Operation When Both Transmission and Reception Are Permitted 10.4.5 Action to Be Taken When the Serial Clock and Shift Become Asynchronous 10.5 SBI MODE 10.5.1 Features of SBI Page 10.5.2 Configuration of the Serial Interface 271 Fig. 10-9 Block Diagram of Clock Synchronous Serial Interface Selector 10.5.3 Detecting an Address Match 10.5.4 Control Registers in SBI Mode 273 Fig. 10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM) 274 275 Fig. 10-11 Format of SBIC Register (2/2) Page 10.6 SBI COMMUNICATION AND SIGNALS 10.6.1 Bus Release Signal (REL) 10.6.2 Command Signal (CMD) 10.6.3 Address 10.6.4 Command and Data 10.6.5 Acknowledge Signal (ACK) 10.6.6 Busy Signal (BUSY) and Ready Signal (READY) 10.6.7 Signals 281 Fig. 10-23 ACKT Operation (c) When ACKE is set to 0 at the end of transfer Fig. 10-24 ACKE Operations (a) When ACKE is set to 1 at the end of transfer (b) When ACKE is set after transfer has been completed 282 (d) When ACKE is set to 1 for a short period of time (b) When the ACK signal is output after the ninth pulse of the SCK clock (c) Clear timing when a transfer start is specified in the busy state 283 Fig. 10-26 BSYE Operation 284 Table 10-2 Signals in SBI Mode (1/3) 285 Table 10-2 Signals in SBI Mode (2/3) 286 Table 10-2 Signals in SBI Mode (3/3) 10.6.8 Communication 10.6.9 Releasing the Busy State 10.6.10 Setting Wake-Up 10.6.11 Starting Transmission and Reception 288 Fig. 10-27 Sending an Address from Master Device to Slave Device 289 Fig. 10-28 Sending a Command from Master Device to Slave Device 290 Fig. 10-29 Sending Data from Master Device to Slave Device 291 Fig. 10-30 Sending Data from the Slave Device to the Master Device 10.7 NOTES CHAPTER 11 EDGE DETECTION FUNCTION 11.1 EXTERNAL INTERRUPT MODE REGISTERS (INTM0, INTM1) 294 Fig. 11-1 Format of External Interrupt Mode Register 0 (INTM0) 295 Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1) 296 11.2 EDGE DETECTION ON PIN P20 s is required to detect the edge. Fig. 11-3 Edge Detection on Pin P20 11.3 EDGE DETECTION ON PINS P21 TO P26 11.4 NOTES Page Page CHAPTER 12 INTERRUPT FUNCTIONS 302 12.1 INTERRUPT REQUEST SOURCES The 12.1.1 Software Interrupt Request 12.1.2 Nonmaskable Interrupt Request 12.1.3 Maskable Interrupt Request 12.1.4 Selecting an Interrupt Source 12.2 INTERRUPT HANDLING CONTROL REGISTERS 305 Table 12-3 Flags for Interrupt Request Sources ) ) 12.2.1 Interrupt Request Flag Register (IF0) 12.2.2 Interrupt Mask Register (MK0) 12.2.3 Interrupt Service Mode Register (ISM0) 12.2.4 Priority Specification Flag Register (PR0) 12.2.5 Interrupt Status Register (IST) 12.2.6 Program Status Word (PSW) 12.3 INTERRUPT HANDLING 12.3.1 Accepting Software Interrupts 12.3.2 Accepting Nonmaskable Interrupts Page 310 12.3.3 Accepting Maskable Interrupts 312 Fig. 12-10 Interrupt Handling Algorithm 12.3.4 Multiple-Interrupt Handling 314 315 12.3.5 Interrupt Request and Macro Service Pending 12.3.6 Interrupt and Macro Service Operation Timing 318 319 12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline 12.4.2 Macro Service Types 12.4.3 Macro Service Basic Operation 322 12.4.4 Macro Service Control Register (1) Macro service control word The macro service function of the 12.4.5 Macro Service Type A 324 Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) Table 12-9 Illegal Write Access Conditions and Corresponding Operations 325 Fig. 12-18 Flow of Data Transfer by Macro Service (Type A) Page 12.4.6 Type B Macro Service 328 Fig. 12-21 Flow of Data Transfer by Macro Service (Type B) Page 330 Fig. 12-24 Parallel Data Input Timing 12.4.7 Macro Service Type C 332 Fig. 12-25 Flow of Data Transfer by Macro Service (Type C) Page Page 335 (b) With ring control 336 Page Page 339 340 341 342 12.5 NOTES Page Page 346 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM) 13.1.2 Programmable Wait Control Register (PW) 13.2 MEMORY EXPANSION FUNCTION 13.2.1 External Memory Expansion Function 348 Fig. 13-3 Read Timing Fig. 13-4 Write Timing 13.2.2 1M-Byte Expansion Function 349 Fig. 13-5 Accessing Expansion Data Memory (a) Read cycle (b) Write cycle 13.2.3 Memory Mapping with Expanded Memory 351 Fig. 13-6 Data Memory Expansion for PD78212 (When EA = L) 352 Fig. 13-7 Data Memory Expansion for PD78212 (When EA = H) 353 PD78213 and Fig. 13-8 Data Memory Expansion for PD78214 (When EA = L) 354 PD78214 and Fig. 13-9 Data Memory Expansion for PD78P214 (When EA = H) 13.2.4 Example of Connecting Memories 356 Fig. 13-10 Example of Connecting Memories to PD78214 13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION 13.4 WAIT FUNCTION 358 Fig. 13-11 Wait Control Space of PD78212 (When EA = L) 359 Fig. 13-12 Wait Control Space of PD78212 (When EA = H) 360 PD78213 and Fig. 13-13 Wait Control Space of PD78214 (When EA = L) 361 PD78214 and Fig. 13-14 Wait Control Space of PD78P214 362 Fig. 13-15 Read Timing of Programmable Wait Function (1/2) (a) When zero wait states are set (b) When one wait state is set 363 Fig. 13-15 Read Timing of Programmable Wait Function (2/2) (c) When two wait states are set 364 Fig. 13-16 Write Timing of Programmable Wait Function (1/2) (a) When zero wait states are set (b) When one wait state is set 365 Fig. 13-16 Write Timing of Programmable Wait Function (2/2) (c) When two wait states are set 366 Fig. 13-17 Timing When External Wait Signal Is Used (a) Read timing (b) Write timing 13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function 13.5.2 Refresh Mode Register (RFM) 13.5.3 Operation Page Page 371 Fig. 13-22 Return from Self-Refresh 13.5.4 Example of Connecting Pseudo Static RAM 13.6 NOTES Page Page 375 Fig. 13-27 Preventing Problems That May Occur during Emulation Page CHAPTER 14 STANDBY FUNCTION 14.1 FUNCTION OVERVIEW 378 Fig. 14-2 Standby Function Block 379 14.2 STANDBY CONTROL REGISTER (STBC) 14.3 HALT MODE 14.3.1 Specifying HALT Mode and Operation States in HALT Mode Table 14-1 Operation States in HALT Mode 380 14.3.2 Releasing HALT Mode Page 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode 14.4.2 Releasing STOP Mode Page 14.4.3 Notes on Using STOP Mode Page 14.5 NOTES 387 Fig. 14-9 Example of Longer Oscillation Settling Time Page CHAPTER 15 RESET FUNCTION 15.1 RESET FUNCTION 390 Table 15-1 Pin States during Reset and After Reset State Is Released 391 Chapter 15 Reset Function Table 15-2 Hardware States after Reset (1/2) 392 Table 15-2 Hardware States after Reset (2/2) Chapter 15 Reset Function 15.2 NOTE Page 16 CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS 396 Fig. 16-1 Example of Controlling Two Stepper Motors Chapter 16 Application Examples 16 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES 398 Fig. 16-3 Example of Communication with SBI Fig. 16-4 Serial Bus Communication Timing 17 CHAPTER 17 PROGRAMMING FOR THE PD78P214 17.1 OPERATING MODE 17.2 PROCEDURE FOR WRITING INTO PROM 400 Fig. 17-1 Timing Chart for PROM Write and Verify Chapter 17 Programming for The PD78214 17 17.3 PROCEDURE FOR READING FROM PROM 17.4 NOTE CHAPTER 18 INSTRUCTION OPERATIONS 18.1 LEGEND 18.1.1 Operand Field 18.1.2 Operation Field 18.1.3 Flag Field 406 18.2 LIST OF OPERATIONS (1) 8-bit data transfer instructions: MOV, XCH 407 (2) 16-bit data transfer instructions: MOVW (3) 8-bit arithmetic/logical instructions: ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP Page 409 (4) 16-bit arithmetic/logical instructions: ADDW, SUBW, CMPW 410 (5) Multiply/divide instructions: MULU, DIVUW (7) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4 (6) Increment/decrement instructions: INC, DEC, INCW, DECW 411 (8) BCD conversion instructions: ADJBA, ADJBS (9) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1 Page 413 (10) Call/return instructions: CALL, CALLF, CALLT, BRK, RET, RETI, RETB (12) Unconditional branch instruction: BR (11) Stack manipulation instructions: PUSH, POP, MOVW, INCW, DECW 414 (13) Conditional branch instructions: BC, BL, BNC, BNL, BZ, BE, BNZ, BNE, BT, BF, BTCLR, DBNZ 415 (14) CPU control instructions: MOV, SEL, NOP, EI, DI 416 18.3 INSTRUCTION LISTS FOR EACH ADDRESSING TYPE 417 418 Page Page Page Page Page Page Page Page Page Page Page 430 it is used as a stand-alone emulator. When the in-circuit emulator is connected to the console so that When the in-circuit emulator is connected to the host mahine DEVELOPMENT ENVIRONMENT B.1 HARDWARE (1/2) HARDWARE (2/2) B.2 SOFTWARE B.2.1 Language Processing Software (1/3) Language Processing Software (2/3) Language Processing Software (3/3) B.2.2 Software for the In-Circuit Emulator (1/2) Software for the In-Circuit Emulator (2/2) () 437 B.2.3 Software for the PROM Programmer B.2.4 OS for the IBM PC The following OSs are supported for the IBM PC: 438 B.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVEL B.3.1 Upgrading to IE-78240-R-A Level B.3.2 Upgrading to IE-78240-R LevelNote 1 (Upgrading to IE-78240-R-A Level is recommended.) B.3.3 Upgrading to IE-78210-R LevelNote 2 (Upgrading to IE-78240-R-A level is recommended.) C APPENDIX C SOFTWARE FOR EMBEDDED APPLICATIONS C.1 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM Page D APPENDIX D REGISTER INDEX D.1 REGISTER INDEX Page Appendix D Register Index D D.2 REGISTER SYMBOL INDEX Page APPENDIX E INDEX E.1 INDEX Page Page Page Page E.2 SYMBOL INDEX