380

µ
PD78214 Sub-Series
14.3.2 Releasing HALT Mode

HALT mode can be released by any of the following three sources:

•Nonmaskable interrupt request (NMI)

•Maskable interrupt request (vectored interrupt or macro service)

•RESET input

Table 14-2 lists the sources used for releasing HALT mode and the operations that are performed after HALT mode

is released by each source.

Table 14-2 Sources for Releasing HALT Mode and Operations Performed after Release

Operation
Ordinary reset operation
Releasing source MK××
RESET input
Nonmaskable
interrupt request
Maskable
vectored interrupt
request
×
0
0
0
0
0
1
PR×× IE ISP
×
×
1
×
1
0
×
×
1
1
0
0
×
×
×
0
×
0
×
1
×
Handling a vectored interruptNote
Executing the macro service
When the end conditions are satisfied, a vectored interrupt
is handled.
When the end conditions are not satisfied, HALT mode is
resumed.
Macro service
request
—××—
Executing the instruction at the next address (holding the
interrupt request)
Executing the macro service
When the end conditions are satisfied, the instruction at the
next address is executed.
When the end conditions are not satisfied, HALT mode is
resumed.
Executing the macro service then resuming HALT mode
(holding the interrupt request)
Continuing HALT mode
0
0
0
0
0
1
1
1
0
0
×
×
0
×
0
×
1
×
×
1
×
1
0
×
Continuing HALT mode (holding the interrupt request)
Handling a vectored interrupt
Note When the NMIS bit of the interrupt status register (LST) is set to 1, the instruction at the next address is executed. Processing then
branches to the NMI interrupt service program when NMIS is cleared to 0.
Remark MK×× : Interrupt mask flag
PR×× : Priority designation flag
IE : Interrupt request enable flag
ISP : Interrupt priority status flag

(1) Release by a nonmaskable interrupt (NMI) request

When a nonmaskable interrupt (NMI) is requested, HALT mode is released regardless of whether interrupts

are enabled (EI) or disabled (DI).

Once HALT mode has been released, processing branches to the NMI service program if the NMIS bit of the

interrupt status register (IST) is set to 0. If the NMIS bit is set to 1 (for example, when HALT mode is specified

in the NMI interrupt service program), processing is resumed from the instruction subsequent the one that

has specified HALT mode. Processing then branches to the NMI interrupt service program when the NMIS

bit is set to 0 (for example, with a RETI instruction).