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Chapter 7 Timer/Counter Units
7
(c) When the value of TM0 is FFFFH
Count clock
fCLK/8
TM0
Cleared by software
OVF0
FFFEH
FFFFH
0H 1H
OVF0←0
(2) Clear operation
After a coincidence with the CR01 compare register, 16-bit timer 0 (TM0) can be automatically cleared. If a
TM0 clear cause occurs, TM0 is cleared to 0000H by the next count clock pulse. This means that even if a TM0
clear cause occurs, TM0 holds the value existing at that time until the next count clock pulse is applied.
Fig. 7-7 TM0 Cleared by a Coincidence with Compare Register (CR01)
Count clock
Compare register
(CR01)
TM0 n-1 n 0 1
Coincidence between
TM0 and CR01
Cleared here
n
TM0 can also be cleared by software when the CE0 bit of the timer control register (TMC0) is reset to 0.
Similarly, clear operation is performed by the count clock pulse following the resetting of CE0 bit to 0. If the
CE0 bit is set to 1 before TM0 is reset to 0 by the resetting of the CE0 bit to 0 (that is, before the first count clock
pulse is applied after the CE0 bit is reset to 0), two operations are simultaneously performed: one operation
is an operation to clear TM0 to 0, and the other operation is a count operation starting with the counting of
0.