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PD78214 Sub-Series
(3) Shift register (SIO)
This 8-bit shift register is used for parallel-serial conversion.
The data written into the SIO is output to the serial data bus. The data on the serial data bus is read into the
SIO. Fig. 10-12 shows the configuration of the shift register and related components.
Fig. 10-12 Configuration of Shift Register and Related Components
In the SBI data bus configuration, the same pins are used for both input and output. The output pin functions
as an N-ch open-drain output pin. With an external pull-up resistor, the output pin has a wired-OR
configuration. For a device that is going to receive data, set the shift register (SIO) to FFH. Alternatively,
disable transmission by the device.
Internal bus
SET CLR
CLK
DQ
BUSY/ACK
Shift clock
N-ch open-drain output
Wired-OR connection
Shift register (SIO)
8
RELT
CMDT
SO latch