232

µ
PD78214 Sub-Series

(3) A/D conversion time

The time required for A/D conversion is determined by the system clock frequency (fCLK) and the FR bit of the

ADM register. To maintain A/D conversion accuracy above a certain level, it is necessary to set the FR bit as

listed in Table 8-2 according to the system clock frequency.

This A/D conversion time includes all the time required for one A/D conversion sequence and the sampling

time.

Table 8-2 shows the conversion time and sampling time.

Table 8-2 A/D Conversion Time

4 MHz < fCLK 6 MHz
2 MHz fCLK 4 MHz
0
1
180/fCLK (30
µ
s to 45
µ
s)
120/fCLK (30
µ
s to 60
µ
s)
36/fCLK (6
µ
s to 9
µ
s)
24/fCLK (6
µ
s to 12
µ
s)
System clock (fCLK)
range FR bit Conversion time Sampling time
8.3.2 Select Mode

Bits 1 through 3 (ANI0 through ANI2) of the ADM register specify one analog input pin. A/D conversion is repeated

for the specified pin. The resultant digital data is stored in the A/D conversion result register (ADCR).

If bit 6 (TRG) of the ADM register is set to enable an external trigger, an A/D conversion end interrupt request

(INTAD) is generated.

Fig. 8-6 Select Mode Operation Timing

(a) TRG bit 0

A/D
conversion
Conversion starts
CS1
MS1
ANI2-0011
ADCR AN3 AN3 AN3
AN3AN3AN3 AN3
AN3 AN3
AN3
AN3

(b) TRG bit 1

AN0
AN0 AN0 AN0
Conversion starts
AN0 AN0 AN0 AN0 AN0 AN0
CS1
MS1
ANI2-0000
AN0
Initialization Initialization Initialization
INTP5
A/D
conversion
ADCR
INTAD
Conversion
end
Conversion
end
Conversion
end
Conversion
end
Conversion
end