NXP Semiconductors PCA9665 manuals

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1. General description
2. Features
PCA9665
- Rev. 02 7 December 2006 Product data sheet
- Fm+ parallel bus to I2C-bus controller
  - Fm+ parallel bus to I2C-bus controller
- 23. Applications
- 4. Ordering information
  - T
  - C
- 35. Block diagram
  - Fig 1. Block diagram of PCA9665
- 46. Pinning information
  - 6.1 Pinning
    - PCA9665N
    - PCA9665PW
    - Fig 4. Pin conguration of DIP20 Fig 5. Pin conguration of HVQFN20
    - Fig 2. Pin conguration of SO20 Fig 3. Pin conguration of TSSOP20
      - PCA9665D
      - PCA9665BS
  - 5NXP Semiconductors PCA9665
  - 6.2 Pin description
  - NXP Semiconductors PCA9665
- 67. Functional description
  - 7.1 General
  - 7.2 Internal oscillator
  - 7.3 Registers
    - Product data sheet Rev. 02 7 December 2006 7 of 91
    - 7Fig 6. Register mapping owchart
    - 87.3.1 Direct registers
  - 9NXP Semiconductors PCA9665
  - 10
  - - 127.3.2 Indirect registers
  - 14
- 168. PCA9665 modes
  - 8.1 Conguration modes
    - 8.1.1 Byte mode
    - 8.1.2 Buffered mode
  - 8.2 Operating modes
  - 178.3 Byte mode
    - 8.3.1 Master Transmitter Byte mode
  - - 19Fig 7. Format and states in the Master Transmitter Byte mode (MODE =0)
    - 8.3.2 Master Receiver Byte mode
  - 22
    - 23Fig 8. Format and states in the Master Receiver Byte mode (MODE = 0)
    - 8.3.3 Slave Receiver Byte mode
  - 25
    - 26Fig 9. Format and states in the Slave Receiver Byte mode (MODE = 0)
    - 298.3.4 Slave Transmitter Byte mode
  - 318.4 Buffered mode
    - 8.4.1 Master Transmitter Buffered mode
  - - 33Fig 11. Format and states in the Master Transmitter Buffered mode (MODE= 1)
    - 8.4.2 Master Receiver Buffered mode
  - 36
    - 37Fig 12. Format and states in the Master Receiver Buffered mode (MODE= 1)
    - 8.4.3 Slave Receiver Buffered mode
  - 40
    - 41Fig 13. Format and states in the Slave Receiver Buffered mode (MODE= 1)
    - 458.4.4 Slave Transmitter Buffered mode
  - 488.5 Buffered mode examples
    - 8.5.1 Buffered Master Transmitter mode of operation
    - 8.5.2 Buffered Master Receiver mode of operation
    - 498.5.3 Buffered Slave Transmitter mode
    - 508.5.4 Buffered Slave Receiver mode
  - 518.6 I2CCOUNT register
  - 538.7 Acknowledge management (I2C-bus addresses and data) in Byte and Buffered modes
  - 56
  - 578.8 Miscellaneous states
    - 8.8.1 I2CSTA= F8h
    - 8.8.2 I2CSTA= 00h
    - 8.8.3 I2CSTA= 70h
    - 8.8.4 I2CSTA= 78h
  - 588.9 Some special cases
    - 8.9.1 Simultaneous repeated START conditions from two masters
    - 8.9.2 Data transfer after loss of arbitration
    - 8.9.3 Forced access to the I2C-bus
    - 598.9.4 I2C-bus obstructed by a LOW level on SCL or SDA
    - 8.9.5 Bus error
  - 608.10 Power-on reset
  - 618.11 Reset
    - Reset of the PCA9665 to its default state can be performed in 2 different ways:
      - Fig 19. Bus timing diagram; Unbuffered Master Transmitter mode
      - Fig 18. Parallel Software Reset sequence
  - 8.12 I2C-bus timing diagrams, Unbuffered mode
    - Master PCA9665 writes data to slave transmitter.
    - Master PCA9665 reads data from slave transmitter.
    - 62Fig 20. Bus timing diagram; Unbuffered Master Receiver mode
      - External master receiver reads data from PCA9665.
    - Fig 22. Bus timing diagram; Unbuffered Slave Receiver mode
    - Fig 21. Bus timing diagram; Unbuffered Slave Transmitter mode
      - Slave PCA9665 is written to by external master transmitter.
  - 638.13 I2C-bus timing diagrams, Buffered mode
    - Fig 24. Bus timing diagram; Buffered Master Receiver mode
    - Fig 23. Bus timing diagram; Buffered Master Transmitter mode
      - External master receiver reads data from PCA9665.
    - 64Fig 25. Bus timing diagram; Buffered Slave Transmitter mode
      - (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]68).
    - Fig 27. Bus timing diagram; Software Reset Call
    - Fig 26. Bus timing diagram; Buffered Slave Receiver mode
      - Slave PCA9665 is written to by external master transmitter.
      - (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]68).
  - NXP Semiconductors PCA9665
- 659. Characteristics of the I2C-bus
  - 9.1 Bit transfer
    - 9.1.1 START and STOP conditions
  - 9.2 System conguration
  - 66NXP Semiconductors PCA9665
  - 9.3 Acknowledge
- 6710. Application design-in information
  - 80C51
  - Fig 32. Application diagram using the 80C51
  - 10.1 Specic applications
  - 10.2 Add I2C-bus port
  - 6810.3 Add additional I2C-bus ports
    - Fig 33. Adding I2C-bus port application
    - Fig 35. Converting parallel to serial data application
    - Fig 34. Adding additional I2C-bus ports application
  - 10.4 Convert 8 bits of parallel data into I2C-bus serial data stream
    - PCA9665
- 6911. Limiting values
  - In accordance with the Absolute Maximum Rating System (IEC 60134).
- 7012. Static characteristics
  - =
  - = 2.3 V to 3.6 V; T
  - C; unless otherwise specied.
- 7113. Dynamic characteristics
  - = 3.3 V
  - 0.3 V; T
  - C; unless otherwise specied. (See Table50 on page 72 for 2.5 V)
  - 72= 2.5 V
  - 0.2 V; T
  - C; unless otherwise specied. (See Table49 on page 71 for 3.3V)
    - 73Fig 36. Reset timing
    - Fig 37. Interrupt timing
    - 74Fig 38. Bus timing (read cycle)
    - Fig 39. Parallel bus timing (write cycle)
      - VM=1.5 V VX=V
    - 75Fig 40. Data timing
      - VY=V
      - VOL and VOH are typical output voltage drops that occur with the output load.
  - 76All the timing limits are valid within the operating supply voltage and ambient temperature range; V
  - = 2.5 V
  - 0.2 V and 3.3 V
  - 0.3 V; T
  - C; and refer to V
  - and V
  - with an input voltage of V
  - to V
  - .
    - 77Fig 41. Denition of timing on the I2C-bus
      - Rise and fall times refer to VIL and VIH.
    - Fig 42. I2C-bus timing diagram
- 7814. Test information
  - V
  - DUT
  - V
    - 002aac695
  - PULSE GENERATOR
    - 002aac694
  - V
  - DUT
  - VDD 2 open V
  - PULSE GENERATOR
  - V
  - open V
- 7915. Package outline
  - DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
    - Fig 45. Package outline SOT146-1 (DIP20)
    - Fig 46. Package outline SOT163-1 (SO20)
  - 80SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
    - Fig 47. Package outline SOT360-1 (TSSOP20)
      - 110
      - 20 11
  - 81TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
  - 82SOT662-1
    - Fig 48. Package outline SOT662-1 (HVQFN20)
- 8316. Handling information
- 17. Soldering
  - 17.1 Introduction
  - 17.2 Through-hole mount packages
    - 17.2.1 Soldering by dipping or by solder wave
    - 17.2.2 Manual soldering
  - 17.3 Surface mount packages
    - 17.3.1 Reow soldering
  - - 84AN10365 Surface mount reow soldering description
    - 17.3.2 Wave soldering
  - 85
    - 17.3.3 Manual soldering
  - 17.4 Package related soldering information
- 8718. Abbreviations
- 19. Revision history
- 8920. Legal information
  - 20.1 Data sheet status
  - 20.2 Denitions
  - 20.3 Disclaimers
  - 20.4 Trademarks
- 21. Contact information
  - continued >>
- 9022. Contents