NXP Semiconductors PCA9665 All the timing limits are valid within the operating supply voltage and ambient temperature range; V, = 2.5 V, 0.2 V and 3.3 V, 0.3 V; T, C; and refer to V, and V, with an input voltage of V, to V, .

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 76 of 91
NXP Semiconductors PCA9665
Fm+ parallel bus to I2C-bus controller
[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25ms. Disable bus time-out feature for DC operation.
[2] tVD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] tVD;DAT= minimum time for SDA data out to be valid following SCL LOW.
[4] Cb=total capacitance of one bus line in pF.
[5] A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tf is specified at
250ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Table 51. I2C-bus frequency and timing specifications
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
= 2.5 V ± 0.2 V and
3.3 V
± 0.3 V; T
amb
= − 40 ° C to +85 ° C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
.
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Fast-mode Plus I2C-bus Unit
Min Max Min Max Min Max
fSCL SCL clock frequency [1] 0 100 0 400 0 1000 kHz
tBUF bus free time between a
STOP and START
condition
4.7 - 1.3 - 0.5 - µs
tHD;STA hold time (repeated)
START condition 4.0 - 0.6 - 0.26 - µs
tSU;STA set-up time for a
repeated START
condition
4.7 - 0.6 - 0.26 - µs
tSU;STO set-up time for STOP
condition 4.0 - 0.6 - 0.26 - µs
tHD;DAT data hold time 0 - 0 - 0 - ns
tVD;ACK data valid acknowledge
time
[2] 0.05 3.45 0.05 0.9 0.05 0.45 µs
tVD;DAT data valid time [3] 50 - 50 - 50 - ns
tSU;DAT data set-up time 250 - 100 - 50 - ns
tLOW LOW period of the SCL
clock 4.7 - 1.3 - 0.5 - µs
tHIGH HIGH period of the SCL
clock 4.0 - 0.6 - 0.26 - µs
tffalltime of both SDA and
SCL signals
[5][6] - 300 20 + 0.1Cb[4] 300 - 120 ns
trrisetime of both SDA and
SCL signals - 1000 20 + 0.1Cb[4] 300 - 120 ns
tSP pulsewidth of spikes that
must be suppressed by
the input filter
[7] - 50 - 50 - 50 ns