NXP Semiconductors PCA9665 13. Dynamic characteristics

PCA9665_2 © NXP B.V. 2006. All rights reserved.

Product data sheet Rev. 02 — 7 December 2006 71 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

13. Dynamic characteristics

[1] Parameters are valid over speciﬁed temperature and voltage range.

[2] All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0V and 3.0 V with a transition time of

5ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 38 and Figure 40.

[3] Test conditions for outputs: CL=50 pF; RL=500Ω, except open-drain outputs.

Test conditions for open-drain outputs: CL=50 pF; RL=1kΩ pull-up to VDD.

[4] Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.

[5] Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

[6] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA and SCL bus.

Table 49. Dynamic characteristics (3.3 volt)[1][2][3]

V

CC

= 3.3 V

±

0.3 V; T

amb

=

−

40

°

C to +85

°

C; unless otherwise speciﬁed. (See Table50 on page 72 for 2.5 V)

Symbol Parameter Conditions Min Typ Max Unit

Initialization timing

tinit(po) power-on initialization time - - 550 µs

Serial interface initialization timing

tinit(sintf) serial interface initialization time[4] from ENSIO bit HIGH - - 550 µs

RESET timing (see Figure36)

tw(rst) reset pulse width 10 - - ns

trst reset time [5][6] 250 - - ns

trec(rst) reset recovery time 0 - - ns

INT timing (seeFigure 37)

tas(int) interrupt assert time - - 500 ns

tdas(int) interrupt de-assert time - - 20 ns

Bus timing (seeFigure 38 and Figure 40)

tsu(A) address setup time to RD,WR LOW 0 - - ns

th(A) address hold time fromRD, WR LOW 13 - - ns

tsu(CE_N) CE setup time to RD,WR LOW 0 - - ns

th(CE_N) CE hold time fromRD, WR LOW 0 - - ns

tw(RDL) RD LOW pulse width 20 - - ns

tw(WRL) WR LOW pulse width 20 - - ns

td(DV) data valid delay time afterRD and CE LOW - - 17 ns

td(QZ) data output ﬂoat delay time afterRD or CE HIGH - - 17 ns

tsu(Q) data output setup time beforeWR or CE HIGH (write cycle) 12 - - ns

th(Q) data output hold time afterWR HIGH 0 - - ns

tw(RDH) RD HIGH pulse width 18 - - ns

tw(WRH) WR HIGH pulse width 18 - - ns

Contents

Main 1. General description 2. Features PCA9665 Rev. 02 7 December 2006 Product data sheet Fm+ parallel bus to I2C-bus controller Fm+ parallel bus to I2C-bus controller 3. Applications 4. Ordering information T C 5. Block diagram Fig 1. Block diagram of PCA9665 6. Pinning information 6.1 Pinning PCA9665N PCA9665PW Fig 4. Pin conguration of DIP20 Fig 5. Pin conguration of HVQFN20 NXP Semiconductors PCA9665 6.2 Pin description NXP Semiconductors PCA9665 7. Functional description 7.1 General 7.2 Internal oscillator 7.3 Registers Product data sheet Rev. 02 7 December 2006 7 of 91 Fig 6. Register mapping owchart 7.3.1 Direct registers NXP Semiconductors PCA9665 Page 7.3.2 Indirect registers Page Page Page 8. PCA9665 modes 8.1 Conguration modes 8.1.1 Byte mode 8.1.2 Buffered mode 8.2 Operating modes 8.3 Byte mode 8.3.1 Master Transmitter Byte mode Page Fig 7. Format and states in the Master Transmitter Byte mode (MODE =0) Page Page 8.3.2 Master Receiver Byte mode Fig 8. Format and states in the Master Receiver Byte mode (MODE = 0) Page 8.3.3 Slave Receiver Byte mode Fig 9. Format and states in the Slave Receiver Byte mode (MODE = 0) Page Page 8.3.4 Slave Transmitter Byte mode Page 8.4 Buffered mode 8.4.1 Master Transmitter Buffered mode Page Fig 11. Format and states in the Master Transmitter Buffered mode (MODE= 1) Page Page 8.4.2 Master Receiver Buffered mode Fig 12. Format and states in the Master Receiver Buffered mode (MODE= 1) Page Page 8.4.3 Slave Receiver Buffered mode Fig 13. Format and states in the Slave Receiver Buffered mode (MODE= 1) Page Page Page 8.4.4 Slave Transmitter Buffered mode Page Page 8.5 Buffered mode examples 8.5.1 Buffered Master Transmitter mode of operation 8.5.2 Buffered Master Receiver mode of operation 8.5.3 Buffered Slave Transmitter mode 8.5.4 Buffered Slave Receiver mode 8.6 I2CCOUNT register Page 8.7 Acknowledge management (I2C-bus addresses and data) in Byte and Buffered modes Page Page Page 8.8 Miscellaneous states 8.8.1 I2CSTA= F8h 8.8.2 I2CSTA= 00h 8.8.3 I2CSTA= 70h 8.8.4 I2CSTA= 78h 8.9 Some special cases 8.9.1 Simultaneous repeated START conditions from two masters 8.9.2 Data transfer after loss of arbitration 8.9.3 Forced access to the I2C-bus 8.9.4 I2C-bus obstructed by a LOW level on SCL or SDA 8.9.5 Bus error 8.10 Power-on reset 8.11 Reset Reset of the PCA9665 to its default state can be performed in 2 different ways: Fig 19. Bus timing diagram; Unbuffered Master Transmitter mode Fig 18. Parallel Software Reset sequence Fig 20. Bus timing diagram; Unbuffered Master Receiver mode External master receiver reads data from PCA9665. Fig 22. Bus timing diagram; Unbuffered Slave Receiver mode Fig 21. Bus timing diagram; Unbuffered Slave Transmitter mode Slave PCA9665 is written to by external master transmitter. 8.13 I2C-bus timing diagrams, Buffered mode Fig 24. Bus timing diagram; Buffered Master Receiver mode Fig 23. Bus timing diagram; Buffered Master Transmitter mode External master receiver reads data from PCA9665. Fig 25. Bus timing diagram; Buffered Slave Transmitter mode (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]68). Fig 27. Bus timing diagram; Software Reset Call Fig 26. Bus timing diagram; Buffered Slave Receiver mode Slave PCA9665 is written to by external master transmitter. 9. Characteristics of the I2C-bus 9.1 Bit transfer 9.1.1 START and STOP conditions 9.2 System conguration NXP Semiconductors PCA9665 9.3 Acknowledge 10. Application design-in information 80C51 Fig 32. Application diagram using the 80C51 10.1 Specic applications 10.2 Add I2C-bus port 10.3 Add additional I2C-bus ports Fig 33. Adding I2C-bus port application Fig 35. Converting parallel to serial data application Fig 34. Adding additional I2C-bus ports application 10.4 Convert 8 bits of parallel data into I2C-bus serial data stream 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). 12. Static characteristics = = 2.3 V to 3.6 V; T C; unless otherwise specied. 13. Dynamic characteristics = 3.3 V 0.3 V; T C; unless otherwise specied. (See Table50 on page 72 for 2.5 V) = 2.5 V 0.2 V; T C; unless otherwise specied. (See Table49 on page 71 for 3.3V) Fig 36. Reset timing Fig 37. Interrupt timing Fig 38. Bus timing (read cycle) Fig 39. Parallel bus timing (write cycle) VM=1.5 V VX=V Fig 40. Data timing VY=V VOL and VOH are typical output voltage drops that occur with the output load. All the timing limits are valid within the operating supply voltage and ambient temperature range; V = 2.5 V 0.2 V and 3.3 V 0.3 V; T C; and refer to V Fig 41. Denition of timing on the I2C-bus Rise and fall times refer to VIL and VIH. Fig 42. I2C-bus timing diagram 14. Test information V DUT V 002aac695 15. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 Fig 45. Package outline SOT146-1 (DIP20) Fig 46. Package outline SOT163-1 (SO20) SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 Fig 47. Package outline SOT360-1 (TSSOP20) 110 20 11 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 SOT662-1 Fig 48. Package outline SOT662-1 (HVQFN20) 16. Handling information 17. Soldering 17.1 Introduction 17.2 Through-hole mount packages 17.2.1 Soldering by dipping or by solder wave AN10365 Surface mount reow soldering description 17.3.2 Wave soldering 17.3.3 Manual soldering 17.4 Package related soldering information Page 18. Abbreviations 19. Revision history 20. Legal information 20.1 Data sheet status 20.2 Denitions 20.3 Disclaimers 20.4 Trademarks 22. Contents