Texas Instruments SPRU938B manuals

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When we buy new device such as Texas Instruments SPRU938B we often through away most of the documentation but the warranty. Very often issues with Texas Instruments SPRU938B begin only after the warranty period ends and you may want to find how to repair it or just do some service work. Even oftener it is hard to remember what does each function in Network Card Texas Instruments SPRU938B is responsible for and what options to choose for expected result. Fortunately you can find all manuals for Network Card on our side using links below.

Texas Instruments SPRU938B Manual

Texas Instruments SPRU938B Manual

48 pages378.6 Kb

3Contents
- Preface
7Read This First
- 1 Introduction 1.1 Purpose of the Peripheral
- 1.2 Features
- User's Guide
8VLYNQ Port
- 91.3 Functional Block Diagram
- 1.4 Industry Standard(s) Compliance Statement
- 102 Peripheral Architecture 2.1 Clock Control
- 122.5 VLYNQ Functional Description
  - (FIFO3) (FIFO2) (FIFO0) (FIFO1)
  - 12 VLYNQ Port SPRU938B September 2007Submit Documentation Feedback
  - 132.5.1 Write Operations
  - SPRU938B September 2007 VLYNQ Port 13Submit Documentation Feedback
  - 142.5.2 Read Operations
  - 14 VLYNQ Port SPRU938B September 2007Submit Documentation Feedback
- 162.8 Address Translation
  - 17Figure 7. Example Address Memory Map
- 192.9 Flow Control
- 202.10 Reset Considerations
- 2.11 Interrupt Support
  - 212.11.2 Writes to Interrupt Pending/Set Register
    - INTLOCAL=1 INTLOCAL=0
- 222.12 EDMA Event Support
- 243 VLYNQ Port Registers
- 253.1 Revision Register (REVID)
  - Table 6. Revision Register (REVID) Field Descriptions
- 263.2 Control Register (CTRL)
  - Table 7. Control Register (CTRL) Field Descriptions
  - 27Table 7. Control Register (CTRL) Field Descriptions (continued)
- 283.3 Status Register (STAT)
  - Table 8. Status Register (STAT) Field Descriptions
  - 29Table 8. Status Register (STAT) Field Descriptions (continued)
- 303.4 Interrupt Priority Vector Status/Clear Register (INTPRI)
- 3.5 Interrupt Status/Clear Register (INTSTATCLR)
- 313.6 Interrupt Pending/Set Register (INTPENDSET)
- 3.7 Interrupt Pointer Register (INTPTR)
- 323.8 Transmit Address Map Register (XAM)
- 333.9 Receive Address Map Size 1 Register (RAMS1)
- 3.10 Receive Address Map Offset 1 Register (RAMO1)
- 343.11 Receive Address Map Size 2 Register (RAMS2)
- 3.12 Receive Address Map Offset 2 Register (RAMO2)
- 353.13 Receive Address Map Size 3 Register (RAMS3)
- 3.14 Receive Address Map Offset 3 Register (RAMO3)
- 363.15 Receive Address Map Size 4 Register (RAMS4)
- 3.16 Receive Address Map Offset 4 Register (RAMO4)
- 373.17 Chip Version Register (CHIPVER)
- 3.18 Auto Negotiation Register (AUTNGO)
  - Figure 25. Chip Version Register (CHIPVER)
  - Table 22. Chip Version Register (CHIPVER) Field Descriptions
  - Table 23. Auto Negotiation Register (AUTNGO) Field Descriptions
- 384 Remote Configuration Registers
  - Remote Configuration Registers
  - Table 24. VLYNQ Port Remote Controller Registers
- 39Appendix A VLYNQ Protocol Specifications A.1 Introduction A.2 Special 8b/10b Code Groups
- A.3 Supported Ordered Sets
  - Appendix A
- 40A.4 VLYNQ 2.0 Packet Format
  - VLYNQ 2.0 Packet Format
  - 41Table A-3. Packet Format (10-bit Symbol Representation) Description
- 42A.5 VLYNQ 2.X Packets
  - VLYNQ 2.X Packets
- 44Appendix B Write/Read Performance B.1 Introduction
- B.2 Write Performance
  - Write Performance
  - 45Table B-1. Scaling Factors
  - Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
- 46B.3 Read Performance
- 47Appendix C Revision History
  - 48IMPORTANT NOTICE

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