Bit Field, Aoptdisable | Texas Instruments SPRU938B specification

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			VLYNQ Port Registers
		Table 7. Control Register (CTRL) Field Descriptions (continued)
Bit	Field	Value	Description
7	INT2CFG		Interrupt to configuration register. Determines which register is written with the status contained in
			interrupt packets that are received over the serial interface. Always write 1 to this bit and configure
			the interrupt pointer register to point to the interrupt pending/set register.
		0	Bits[31:2] of the interrupt pointer register are used to point to a system interrupt register.
		1	The least significant 8 bits of the interrupt pointer register are used to point to a VLYNQ module
			local register (typically the interrupt pending/set register).
6-3	Reserved	0	Reserved. Always read as 0. Writes have no effect.
2	AOPTDISABLE		Address optimization disable.
		0	Address optimization is enabled, eliminating unnecessary address bytes.
		1	Address optimization is disabled.
1	ILOOP		Internal loop back.
		0	Normal operation.
		1	Serial transmit data is wrapped back to the serial receive data.
0	RESET		Software reset. It does not reset the VLYNQ memory-mapped registers (except for the VLYNQ
			status register). You have to reprogram the VLYNQ registers if they must have a different value
			after a software reset.
		0	Normal operation.
		1	All internal state machines are reset, the serial interface is disabled, and the link is lost.

SPRU938B –September 2007	VLYNQ Port	27
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Texas Instruments SPRU938B manual Bit Field, Aoptdisable

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block Diagram Clock Control External Clock Block Diagram Protocol Description Signal DescriptionsVlynq Signal Descriptions Pin Multiplexing Vlynq Module Structure Vlynq Functional Description Write Operations Read Operations Auto-Negotiation Initialization Address Translation Register DM643x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM643x Vlynq Module Example 1. Address Translation Example Flow Control Interrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram Serial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address Size Bit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj Revmin Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Instat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Nointpend Intset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field Descriptions Transmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1 RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2 RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3 RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4 Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field Descriptions Vlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered Sets Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZ Latency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies Throughput Reference Additions/Modifications/Deletions Table C-1. Document Revision History Products Applications DSPRfid