Submit Documentation Feedback | Texas Instruments SPRU938B specification

2	SPRU938B –September 2007

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Texas Instruments SPRU938B manual Submit Documentation Feedback

Contents

Users Guide Submit Documentation Feedback Contents Appendix B Appendix C List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement External Clock Block Diagram Clock Control Pin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol Description Vlynq Functional Description Vlynq Module Structure Write Operations Read Operations Initialization Auto-Negotiation Address Translation Address Translation Example Single Mapped Region Register DM643x Vlynq Module DM643x Vlynq Module Remote Vlynq Module Flow Control Example 1. Address Translation Example Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt Support Interrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set Register Remote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register Description Revmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value Description Control Register Ctrl Control Register Ctrl Field Descriptions Aoptdisable Bit Field Status Register Stat Status Register Stat Field Descriptions No error Lerror Nointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Instat Interrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Intset Txadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1 RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2 RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3 RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4 Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field Descriptions Vlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code Groups Figure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet Format Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/sec Throughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsec Table C-1. Document Revision History Reference Additions/Modifications/Deletions Rfid Products ApplicationsDSP