Table C-1. Document Revision History

www.ti.com

Appendix C

Appendix C Revision History

Table C-1lists the changes made since the previous version of this document.

Reference Additions/Modifications/Deletions

Section 2.8 Changed fourth paragraph.

Added NOTE.

Section 3.17 Changed paragraph.

Figure 25 Changed DEVID reset value.

Table 22 Changed DEVID Description.

SPRU938B –September 2007	Revision History	47
Submit Documentation Feedback

Page 47

Image 47

Texas Instruments SPRU938B manual Table C-1. Document Revision History, Reference Additions/Modifications/Deletions

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block Diagram Clock Control External Clock Block Diagram Protocol Description Signal DescriptionsVlynq Signal Descriptions Pin Multiplexing Vlynq Module Structure Vlynq Functional Description Write Operations Read Operations Auto-Negotiation Initialization Address Translation Register DM643x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM643x Vlynq Module Example 1. Address Translation Example Flow Control Interrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram Remote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address Size Bit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj Revmin Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Instat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Nointpend Intset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field Descriptions Txadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1 RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2 RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3 RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4 Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field Descriptions Vlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered Sets Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZ Latency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies Throughput Reference Additions/Modifications/Deletions Table C-1. Document Revision History Rfid Products ApplicationsDSP

Appendix C Revision History

Table C-1. Document Revision History

Reference Additions/Modifications/Deletions

Figure 25 Changed DEVID reset value.

Table 22 Changed DEVID Description.

SPRU938B –September 2007

Submit Documentation Feedback