Texas Instruments SPRU938B manual List of Figures

	List of Figures
1	VLYNQ Port Functional Block Diagram	9
2	External Clock Block Diagram	10
3	Internal Clock Block Diagram	10
4	VLYNQ Module Structure	12
5	Write Operations	13
6	Read Operations	14
7	Example Address Memory Map	17
8	Interrupt Generation Mechanism Block Diagram	21
9	Revision Register (REVID)	25
10	Control Register (CTRL)	26
11	Status Register (STAT)	28
12	Interrupt Priority Vector Status/Clear Register (INTPRI)	30
13	Interrupt Status/Clear Register (INTSTATCLR)	30
14	Interrupt Pending/Set Register (INTPENDSET)	31
15	Interrupt Pointer Register (INTPTR)	31
16	Transmit Address Map Register (XAM)	32
17	Receive Address Map Size 1 Register (RAMS1)	33
18	Receive Address Map Offset 1 Register (RAMO1)	33
19	Receive Address Map Size 2 Register (RAMS2)	34
20	Receive Address Map Offset 2 Register (RAMO2)	34
21	Receive Address Map Size 3 Register (RAMS3)	35
22	Receive Address Map Offset 3 Register (RAMO3)	35
23	Receive Address Map Size 4 Register (RAMS4)	36
24	Receive Address Map Offset 4 Register (RAMO4)	36
25	Chip Version Register (CHIPVER)	37
26	Auto Negotiation Register (AUTNGO)	37
A-1	Packet Format (10-bit Symbol Representation)	40

SPRU938B –September 2007 List of Figures 5

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