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Peripheral Architecture
2.13 Power Management
The VLYNQ module can be placed in reduced-power modes to conserve power during periods of low activity. The power management of the VLYNQ module is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).
The power conservation modes that are available via the PSC are:
∙Idle/Disabled state : Idle/disabled state stops the clocks from going to the peripheral and prevents all of the register accesses. After re-enabling the peripheral from its idle state, all registers prior to setting in the disabled state are restored and data transmission proceeds. Re-initialization is not required.
∙Synchronized reset : The synchronized reset state is similar to the power-on reset (POR) state. When the processor is turned on, reset to the peripheral is asserted, then clocks to the peripheral are gated. Registers reset to their default values. When powering-up after a synchronized reset, all of the VLYNQ module registers must be reconfigured and the link must be re-established before data transmission.
If the serial clock is internally sourced, you can use the CLKDIV bit in the VLYNQ control register (CTRL) to divide the serial clock down. This saves normal mode operation power consumption (at the expense of reduced performance).
Additionally, the module provides the capability of auto-idling the serial clock domain (disable the VLYNQ CLK) when the serial clock is sourced from the DM643x device and the VLYNQ SCRUN pin is connected to the remote device. This allows power savings when there is no activity on the serial interface.
Note: There is no support for external wake-up for the VLYNQ module on the DM643x device. If the VLYNQ module on the DM643x device has been disabled via the PSC, then even though serial activity requests can be indicated from the remote VLYNQ device via the VLYNQ SCRUN pin, it does not allow the serial clock (VLYNQ CLK) to be sourced until the VLYNQ module is re-enabled via the PSC.
This can be configured by enabling the power management enable (PMEN) bit in the VLYNQ control registers (CTRL, 0 = disable, 1 = enable) . This bit should only be set if the SCRUN pin is connected to the remote VLYNQ device.
The SCRUN pin is a bi-directional pin which is driven low whenever there is serial activity on the local or remote VLYNQ interface.
2.14 Endianness Considerations
There are no endianness considerations for the VLYNQ peripheral.
2.15 Emulation Considerations
During debug, the CPU may be halted for single stepping, bench marking, profiling, or other debug uses using the emulator. VLYNQ does not support emulation halts/suspend operation. VLYNQ operations continue during emulation halt/suspend.
SPRU938B –September 2007 | VLYNQ Port | 23 |
