Appendix B, Appendix C | Texas Instruments SPRU938B guide

A.2	Special 8b/10b Code Groups	39
A.3	Supported Ordered Sets	39
A.4	VLYNQ 2.0 Packet Format	40
A.5	VLYNQ 2.X Packets	42
Appendix B	Write/Read Performance	44
B.1	Introduction	44
B.2	Write Performance	44
B.3	Read Performance	46
Appendix C	Revision History	47

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Contents

SPRU938B –September 2007

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Texas Instruments SPRU938B manual Appendix B, Appendix C

Contents

Users Guide Submit Documentation Feedback Contents Appendix B Appendix C List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement External Clock Block Diagram Clock Control Signal Descriptions Vlynq Signal DescriptionsPin Multiplexing Protocol Description Vlynq Functional Description Vlynq Module Structure Write Operations Read Operations Initialization Auto-Negotiation Address Translation Address Translation Example Single Mapped Region Register DM643x Vlynq Module DM643x Vlynq Module Remote Vlynq Module Flow Control Example 1. Address Translation Example Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt Support Interrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set Register Edma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Register Address Space Vlynq Port Controller RegistersBlock Name Start Address End Address Size Acronym Register Description Revision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value Description Control Register Ctrl Control Register Ctrl Field Descriptions Aoptdisable Bit Field Status Register Stat Status Register Stat Field Descriptions No error Lerror Interrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend Instat Interrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions Intset Address Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1 Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2 Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3 Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4 Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field Descriptions Vlynq Port Remote Controller Registers Introduction Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code Groups Figure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet Format Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/sec Read Performance Table B-3. Relative Performance with Various LatenciesThroughput Latency μsec Table C-1. Document Revision History Reference Additions/Modifications/Deletions DSP Products ApplicationsRfid