Functional Block Diagram | Texas Instruments SPRU938B guide

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Introduction

∙Symmetric Operations

–Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device and vice-versa.

–Data pin widths are automatically detected after reset

–Re-request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins.

–Supports both host/peripheral and peer-to-peer communication models

∙Simple block code packet formatting (8b/10b)

∙Supports in-band and flow control

–No extra pins are needed

–Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur

–Uses the special built-in block code capability to interleave flow control information seamlessly with user data

∙Automatic packet formatting optimizations

∙Internal loopback modes are provided

∙Connects to legacy VLYNQ devices

1.3Functional Block Diagram

Figure 1 shows a functional block diagram of the VLYNQ port.

Figure 1. VLYNQ Port Functional Block Diagram

System

CPU/EDMA

System memory

VLYNQregister

access

CPU/EDMA initiated

transfersto

remotedevice

Offchip

(remote)

deviceaccess

VLYNQmodule

Slave config bus Interface

Master

config

bus

Interface

VLQINT

INT55

interruptcontroller

VLYNQ_SCRUN

VLYNQ_CLOCK

VLYNQ_TXD[3:0]

VLYNQ_RXD[3:0]

1.4Industry Standard(s) Compliance Statement

VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.

SPRU938B –September 2007

VLYNQ Port

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Texas Instruments SPRU938B manual Functional Block Diagram, Industry Standards Compliance Statement

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block Diagram Clock Control External Clock Block Diagram Vlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol Description Vlynq Module Structure Vlynq Functional Description Write Operations Read Operations Auto-Negotiation Initialization Address Translation Register DM643x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM643x Vlynq Module Example 1. Address Translation Example Flow Control Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt Support Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram Serial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register Description Revision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value Description Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Interrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend Instat Interrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions Intset Transmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1 Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2 Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3 Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4 Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field Descriptions Vlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code Groups Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZ Table B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsec Reference Additions/Modifications/Deletions Table C-1. Document Revision History Products Applications DSPRfid