Introduction, Supported Ordered Sets | Texas Instruments SPRU938B

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Appendix A

Appendix A VLYNQ Protocol Specifications

A.1 Introduction

VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control. The following sections include general 8b/10b coding definitions and their implementation.

A.2 Special 8b/10b Code Groups

Table A-1. Special 8b/10b Code Groups

Code Group Name	Octet Value	Octet Bits	Current RD -	Current RD +
K28.0	1C	0001 1100	001111 0100	110000 1011
K28.1	3C	0011 1100	001111 1001	110000 0110
K28.2	5C	0101 1100	001111 0101	110000 1010
K28.3	7C	0111 1100	001111 0011	110000 1100
K28.4	9C	1001 1100	001111 0010	110000 1101
K28.5	BC	1011 1100	001111 1010	110000 0101
K28.6	DC	1101 1100	001111 0110	110000 1001
K28.7	FC	1111 1100	001111 1000	110000 0111
K23.7	F7	1111 0111	111010 1000	000101 0111
K27.7	FB	1111 1011	110110 1000	001001 0111
K29.7	FD	1111 1101	101110 1000	010001 0111
K30.7	FE	1111 1110	011110 1000	100001 0111

A.3 Supported Ordered Sets

Each VLYNQ module must support a limited number of ordered sets. Ordered sets provide for the delineation of packets and synchronization between VLYNQ modules at opposite ends of the serial connection. VLYNQ 2.0 and later versions do not require some of the following ordered sets.

Table A-2. Supported Ordered Sets

Code	Ordered Set	Encoding	Octet Value
/I/	Idle	/K28.5/	BC
/T/	End of Packet	/K29.7/	FD
/M/	Byte Disable	/K23.7/	F7
/P/	Flow Control Enable	/K28.0/	IC
/C/	Flow Control Disable	/K28.2/	5C
/E/	Error Indication	/K28.1/	3C
/0/	Init0	/K28.4/	9C
/I/	Init1	/K28.6/	DC
/L/	Link	/K30.7/	FE

SPRU938B –September 2007	VLYNQ Protocol Specifications	39
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Texas Instruments SPRU938B manual Introduction, Special 8b/10b Code Groups, Supported Ordered Sets

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block Diagram Clock Control External Clock Block Diagram Protocol Description Signal DescriptionsVlynq Signal Descriptions Pin Multiplexing Vlynq Module Structure Vlynq Functional Description Write Operations Read Operations Auto-Negotiation Initialization Address Translation Register DM643x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM643x Vlynq Module Example 1. Address Translation Example Flow Control Interrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram Serial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address Size Bit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj Revmin Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Instat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Nointpend Intset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field Descriptions Transmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1 RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2 RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3 RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4 Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field Descriptions Vlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered Sets Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZ Latency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies Throughput Reference Additions/Modifications/Deletions Table C-1. Document Revision History Products Applications DSPRfid