Revision Register Revid, Revmaj Revmin | Texas Instruments SPRU938B

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VLYNQ Port Registers

3.1Revision Register (REVID)

The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVID is shown in Figure 9 and described in Table 6.

Figure 9. Revision Register (REVID)

31			16
		ID
		R-1h
15	8	7	0
	REVMAJ		REVMIN
	R-2h		R-6h

LEGEND: R = Read only; -n= value after reset

			Table 6. Revision Register (REVID) Field Descriptions
Bit	Field	Value	Description
31-16	ID	01h	Unique module ID.
15-8	REVMAJ	0-FFh	Major revision.
		2h	Current major revision.
7-0	REVMIN	0-FFh	Minor revision.
		6h	Current minor revision.

SPRU938B –September 2007	VLYNQ Port	25
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Texas Instruments SPRU938B Revision Register Revid Field Descriptions, Revmaj Revmin, Bit Field Value Description

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block Diagram Clock Control External Clock Block Diagram Vlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol Description Vlynq Module Structure Vlynq Functional Description Write Operations Read Operations Auto-Negotiation Initialization Address Translation Register DM643x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM643x Vlynq Module Example 1. Address Translation Example Flow Control Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt Support Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram Edma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register Description Revision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value Description Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Interrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend Instat Interrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions Intset Address Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1 Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2 Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3 Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4 Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field Descriptions Vlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code Groups Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZ Table B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsec Reference Additions/Modifications/Deletions Table C-1. Document Revision History DSP Products ApplicationsRfid