Abit NI8 SLI user manual Appendix

Models: NI8 SLI

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Appendix I

 

 

 

 

 

 

 

 

 

 

 

1F

Load keyboard matrix (notebook platform)

 

 

21

HPM initialization (notebook platform)

 

 

23

1.

Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute.

 

 

2.

Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value

 

 

 

 

instead.

 

 

24

Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration

 

 

of the ESCD’s legacy information.

 

 

 

Early PCI Initialization:

 

 

25

 

-Enumerate PCI bus number.

 

 

 

-Assign memory & I/O resource

 

 

 

 

 

 

 

 

-Search for a valid VGA device & VGA BIOS, and put it into C000:0

 

 

 

1.

If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization.

 

 

26

 

Disable respective clock resource to empty PCI & DIMM slots.

 

 

2.

Init onboard PWM

 

 

 

3.

Init onboard H/W monitor devices

 

 

27

Initialize INT 09 buffer

 

 

 

1.

Program CPU internal MTRR (P6 & PII) for 0-640K memory address.

 

 

29

2.

Initialize the APIC for Pentium class CPU.

 

 

3.

Program early chipset according to CMOS setup. Example: onboard IDE controller.

 

 

 

 

 

 

4.

Measure CPU speed.

 

 

2B

Invoke Video BIOS

 

 

2D

1.

Initialize double-byte language font (Optional)

 

 

2.

Put information on screen display, including Award title, CPU type, CPU speed, full

 

 

 

 

screen logo.

 

 

33

Reset keyboard if Early_Reset_KB is defined e.g. Winbond 977 series Super I/O chips.

 

 

See also POST 63.

 

 

35

Test DMA Channel 0

 

 

37

Test DMA Channel 1.

 

 

39

Test DMA page registers.

 

 

3C

Test 8254

 

 

3E

Test 8259 interrupt mask bits for channel 1

 

 

40

Test 8259 interrupt mask bits for channel 2

 

 

43

Test 8259 functionality

 

 

47

Initialize EISA slot

 

 

49

1.

Calculate total memory by testing the last double word of each 64K page

 

 

2.

Program writes allocation for AMD K5 CPU

 

 

 

 

 

 

1.

Program MTRR of M1 CPU

 

 

4E

2.

Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range

 

 

3.

Initialize the APIC for P6 class CPU

 

 

 

4.

On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges

 

 

 

 

between each CPU are not identical

 

 

50

Initialize USB

 

 

52

Test all memory (clear all extended memory to 0)

 

 

53

Clear password according to H/W jumper (Optional)

 

 

 

 

 

 

 

 

 

 

 

NI8 SLI Series

Page 76
Image 76
Abit NI8 SLI user manual Appendix