POST Codes Tables
These tables describe the chipset and core POST codes, functions, phases, and components for the POST.
Chipset POST Codes
The following table details the chipset POST codes and functions used in the POST.
POST Code | Function | Phase | Component |
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0xA0 | MRC Entry | PEI | chipset/MRC |
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0x01 | Enable MCHBAR | PEI | chipset/MRC |
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0x02 | Check ME existence | PEI | chipset/MRC |
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0x03 | Check for DRAM initialization interrupt and reset fail | PEI | chipset/MRC |
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0x04 | Determine the system Memory type based on first | PEI | chipset/MRC |
| populated socket |
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0x05 | Verify all DIMMs are DDR2 and | PEI | chipset/MRC |
| are unbuffered |
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0x06 | Verify all DIMMs are | PEI | chipset/MRC |
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0x07 | Verify all DIMMs are single or double sided and not | PEI | chipset/MRC |
| mixed |
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0x08 | Verify all DIMMs are x8 or x16 width | PEI | chipset/MRC |
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0x09 | Calculate number of Row and Column bits | PEI | chipset/MRC |
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0x10 | Calculate number of banks for each DIMM | PEI | chipset/MRC |
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0x11 | Determine raw card type | PEI | chipset/MRC |
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0x12 | Find a common CAS latency between the DIMMS | PEI | chipset/MRC |
| and the MCH |
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0x13 | Determine the memory frequency and CAS latency | PEI | chipset/MRC |
| to program |
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0x14 | Determine the smallest common timing value for all | PEI | chipset/MRC |
| DIMMS |
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0x17 | Power management resume | PEI | chipset/MRC |
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0x18 | Program DRAM type (DDR2/DDR3) and Power up | PEI | chipset/MRC |
| sequence |
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0x19 | Program the correct system memory frequency | PEI | chipset/MRC |
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0x20 | Program the correct Graphics memory frequency | PEI | chipset/MRC |
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0x21 | Early DRC initialization | PEI | chipset/MRC |
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0x22 | Program the DRAM Row Attributes and DRAM Row | PEI | chipset/MRC |
| Boundary registers PRE JEDEC. |
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0x23 | Program the RCOMP SRAM registers | PEI | chipset/MRC |
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0x24 | Program DRAM type (DDR2/DDR3) and Power up | PEI | chipset/MRC |
| sequence |
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0x25 | Program the DRAM Timing | PEI | chipset/MRC |
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0x26 | Program the DRAM Bank Architecture register | PEI | chipset/MRC |
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0x27 | Enable all clocks on populated rows | PEI | chipset/MRC |
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0x28 | Program MCH ODT | PEI | chipset/MRC |
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0x29 | Program tRD | PEI | chipset/MRC |
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0x30 | Miscellaneous Pre JEDEC steps | PEI | chipset/MRC |
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0x31 | Program clock crossing registers | PEI | chipset/MRC |
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Chapter 4 | 133 |
