POST Code | Function | Phase | Component |
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0x4C | Shadow video BIOS ROM if specified by Setup, and | LBT | Core |
| CMOS is valid and the previous boot was OK. |
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0x59 | Register POST Display Services, fonts, and | LBT | Core |
| languages with the POST Dispatch Manager. |
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0x57 | Initialize 1394 Firewire | LBT | Core |
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0xD6 | Initialize PC card | LBT | Core |
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0x58 | Test for unexpected interrupts. First do an STI for hot | LBT | Core |
| interrupts. Secondly, test the NMI for an unexpected |
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| interrupt. Thirdly, enable the parity checkers and |
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| read from memory, checking for an unexpected |
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| interrupt. |
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0x3F | ROMPolit memory init | LBT | Core |
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0xC4 | Install the IRQ vectors (Sever Hotkey) | LBT | Core |
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0x7C | Initialize the hardware interrupt vectors from 08 to 0F | LBT | Core |
| and from 70h to 77H. Also set the interrupt vectors |
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| from 60h to 66H to zero. |
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0x41 | ROM Pilot Init | LBT | Core |
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0x4B | Initialize QuietBoot if it is installed. Enable both | LBT | Core |
| keyboard and timer interrupts (IRQ0 and IRQ1). If |
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| your POST tasks require interrupts off, preserve |
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| them with a PUSHF and CLI at the beginning and a |
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| POPF at the end. |
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0xDE | Initialize and UNDI ROM (fro remote flash) | LBT | Core |
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0xC6 | Initial and install console for UCR | LBT | Core |
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0x4E | Display copyright notice. | LBT | Core |
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0xD4 | Get CPU branding string | LBT | Core |
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0x50 | Display CPU type and speed | LBT | Core |
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0xC9 | pretask before EISA init | LBT | Core |
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0x51 | EISA Init | LBT | Core |
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0x5A | Display prompt "Press F2 to enter SETUP" | LBT | Core |
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0x5B | Disable CPU cache. | LBT | Core |
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0x5C | Test RAM between 512K and 640K. | LBT | Core |
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0x60 | Determine and test the amount of extended memory | LBT | Core |
| available. Determine if memory exists by writing to a |
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| few strategic locations and see if the data can be |
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| read back. If so, perform an |
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| RAM test on the memory. |
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0x62 | The amount of memory available. This test is | LBT | Core |
| dependent on the processor, since the test will vary |
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| depending on the width of memory (16 or 32 bits). |
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| This test will also use A20 as the skew address to |
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| prevent corruption of the system memory. |
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0x64 | Jump to UserPatch1. | LBT | Core |
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0x66 | Set cache registers to their CMOS values if CMOS is | LBT | Core |
| valid, unless auto configuration is enabled, in which |
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| case load cache registers from the Setup default |
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| table. |
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0x68 | Enable external cache and CPU cache if present. | LBT | Core |
| Configure |
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Chapter 4 | 139 |
