![](/images/new-backgrounds/1156533/156533325x1.webp)
Code | Beeps | POST Routine Description |
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|
|
0Ah |
| Initialize CPU registers |
0Bh |
| Enable CPU cache |
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|
|
0Ch |
| Initialize caches to initial POST values |
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|
|
0Eh |
| Initialize I/O component |
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|
|
0Fh |
| Initialize the local bus IDE |
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|
|
10h |
| Initialize Power Management |
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|
|
11h |
| Load alternate registers with initial POST values |
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|
|
12h |
| Restore CPU control word during warm boot |
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|
|
13h |
| Initialize PCI Bus Mastering devices |
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|
|
14h |
| Initialize keyboard controller |
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|
16h | BIOS ROM checksum | |
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|
|
17h |
| Initialize cache before memory autosize |
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|
|
18h | 8254 | timer initialization |
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|
|
1Ah | 8237 | DMA controller initialization |
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|
|
1Ch |
| Reset Programmable Interrupt Controller |
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|
|
20h | Test DRAM refresh | |
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|
|
22h | Test 8742 Keyboard Controller | |
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|
|
24h |
| Set ES segment register to 4 GB |
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|
|
26h |
| Enable A20 line |
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|
|
28h |
| Autosize DRAM |
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|
|
29h |
| Initialize POST Memory Manager |
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|
|
2Ah |
| Clear 512 KB base RAM |
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|
|
2Ch | RAM failure on address line xxxx* | |
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|
|
2Eh | RAM failure on data bits xxxx* of low byte of memory bus | |
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|
|
2Fh |
| Enable cache before system BIOS shadow |
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|
|
30h | RAM failure on data bits xxxx* of high byte of memory bus | |
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|
|
32h |
| Test CPU |
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|
|
33h |
| Initialize Phoenix Dispatch Manager |
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|
|
36h |
| Warm start shut down |
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|
|
38h |
| Shadow system BIOS ROM |
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|
|
3Ah |
| Autosize cache |
|
|
|
3Ch |
| Advanced configuration of chipset registers |
|
|
|
3Dh |
| Load alternate registers with CMOS values |
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|
|
42h |
| Initialize interrupt vectors |
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|
|
45h |
| POST device initialization |
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|
|
46h | Check ROM copyright notice | |
|
|
|
48h |
| Check video configuration against CMOS |
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|
|
49h |
| Initialize PCI bus and devices |
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|
|
4Ah |
| Initialize all video adapters in system |
|
|
|
4Bh |
| QuietBoot start (optional) |
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|
|
4Ch |
| Shadow video BIOS ROM |
|
|
|
4Eh |
| Display BIOS copyright notice |
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|
|
50h |
| Display CPU type and speed |
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|
|
Chapter 4 | 153 |