Section Using System Designer, Description | Atmel STK594 specification

Section 4 Using System Designer

This tutorial will guide you through the required steps for designing and programming

AT94K series devices using System Designer.

4.1Preparing the Before starting the tutorial, a few preparations need to be performed:

Example Files 1. Create a STK594 directory under C:\SystemDesigner\Designs\.

2.Download STK594.ZIP from the FPSLIC software page of the Atmel web site and copy STK594.ZIP to C:\SystemDesigner\Designs\STK594.

3.Extract the contents of the STK594.ZIP file to

C:\SystemDesigner\Designs\STK594.The contents of the zip file are shown in Table 4-1.

File	Description

AT94KDEF.INC	Atmel AVR Assembler AT94K FPSLIC Include File

COUNTER.PIN	FPGA Pin Lock File

COUNTER.V	Top Level FPGA Verilog® Counter Source File
COUNTER.VHD	Top Level FPGA VHDL® Counter Source File
STK594.ASM	Atmel AVR Assembler Source File

4.2	Description	The design in this tutorial is composed of a simple AVR microcontroller program and a
		loadable counter implemented in the FPGA. When the counter reaches the terminal
		value, an interrupt to the microcontroller will be generated using the counter’s carry-out
		(RCO) signal. The interrupt is active Low and must be held for three clock cycles prior to
		its acknowledgement by the microcontroller. During the Interrupt Service Routine (ISR)
		the microcontroller increments the count of interrupt occurrences and places the incre-
		mented data on PORTD and the AVR-FPGA Data Bus, triggering the counter’s LOAD
		signal. Once the counter has been loaded, counting will commence and the process will
		be repeated. Figure 4-1 shows a simplified block diagram of the tutorial design.

FPSLIC STK594 User Guide

4-1

Rev. 2819A–FPSLI–07/02