Using System Designer
FPSLIC STK594 User Guide 4-9
2819A–FPSLI–07/02
3. Connect the counter's
LOAD
signal to
FPGA-AVRI/O Select 0
.
4. Select the
AVRIoSelects
tab on the right-hand side of the dialog box.
5. Select the
LOAD
signal from the
Input Design Ports
and select
IOSELA0
from
the
AVRIoSelects
.
6. Press
Connect
.
7. Connect the remaining inputs and outputs as shown in Table 4-2.
8. Uncheck
Generate Template TestBench File
on the bottom left-hand side of the
Select Ports
dialog. Since we are not performing co-verification, it is not neces-
sary to generate the pre-layout test bench file.
9. Press
OK.
4.8 FPGA Place andRoute
The Figaro Integrated Development System (IDS) is used as the FPGA Place &
Route tool. Figaro takes the gate-level technology-specific file generated by the syn-
thesis tool and partitions, places, and routes the FPGA design.
1. Press the
Figaro IDS
buttontoopenthe
FPGA Place & Route ToolsS ettings
dia-
log, see Figure 4-14.
Figure 4-14.
FPGA Place & Route Tools Settings Dialog
Table 4-2.
FPGA-AVR Interface Connections
FPGA I/O FPGA-AVRI/O Select PortsTab
LOAD OSELA0 AVRIoSelects
RCO INTA0 FPGAInterrupts
D(7:0) ADINA(7:0) DataFromAVR
aWE FIOWEA AVRControls
CLK GCLK5 AVRClocks