================================
FPGA INFORMATION
BOARD VER.: 0x3
PROGRAM VER. : 0x11
DIP SWITCH STATUS 12345678
ON: *
OFF: ****** *
MEMORY SWITCH STATUS
MSW1 12345678
MSW2 12345678
MSW3 12345678
MSW4 12345678
MSW5 12345678
MSW6 12345678
MSW11 12345678
MSW12 12345678
SERIAL SETTING |
|
BAUD RATE | : 115200 BPS |
DATA BITS | : 8 BITS |
PARITY CHECK : NONE | |
STOP BITS | : 1 BIT OR MORE |
HANDSHAKING : DTR/DSR
ETHERNET SETTING
MAC ADDR: 00:11:22:33:44:55 LAN_DHCP disabled
IP ADDR : 192.168.192.123
NETMASK : 255.255.255.0
GATEWAY : 192.168.192.254
WLAN SETTING
NETWORK: adhoc
AUTH: open
ENCRYPT: none
ESSID: BIXOLON_adhoc
WLAN_DHCP disabled
IPADDR: 192.168.1.1
NETMASK: 255.255.255.0
GATEWAY: 192.168.1.2
BUFFER CAPACITY: 512KBYTES
PRINT DENSITY LIGHT [ 1 2 3 4 ] DARK
*
PLEASE PRESS THE FEED BUTTON
SRP-F310/312
ASCII
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Figure 2-10 The Self-Test Sheet
Rev. 1.00 | - 11 - |