Schematic Diagrams
LGA1366 Part B DDR3 2/2
C hannelA
J_C PU 1D
7M_MAA_A[ 15: 0]
7M_SB S_A[2: 0]
7M_SC KE _A [1: 0]
7M_OD T_A[ 1:0]
7CK _M_C H0_0 _D P
7CK _M_C H0_0 _D N
7CK _M_C H0_1 _D P
7CK _M_C H0_1 _D N
CK_M_CH0_2_DP CK_M_CH0_2_DN CK_M_CH0_3_DP CK_M_CH0_3_DN
7M_R AS_A_N
7M_C AS_A_N
7 M_W E_A_N
7M_SC S_A_N 0
7M_SC S_A_N 1
M_SCS_A_N4
M_SCS_A_N5
7 DD R 0_D R AMR ST
M_MA A_A[15:0]
M_S BS_A[ 2:0]
M_S C KE_A[ 1: 0]
M_OD T_A[1: 0]
C K_M_C H 0_0_ DP C K_M_C H 0_0_ DN
C K_M_C H 0_1_ DP C K_M_C H 0_1_ DN
DIMM1 no using
M_R A S_A_N
M_C A S_A_N
M_W E _A _N
M_S C S_A_N 0
M_S C S_A_N 1
DIMM1 no using
D D R0_D RA MR ST
M_MA A_B15
M_MA A_B14
M_MA A_B13
M_MA A_B12
M_MA A_B11
M_MA A_B10
M_MA A_B9
M_MA A_B8
M_MA A_B7
M_MA A_B6
M_MA A_B5
M_MA A_B4
M_MA A_B3
M_MA A_B2
M_MA A_B1
M_MA A_B0
M_SBS_B2
M_SBS_B1
M_SBS_B0
M_RA S_B_N
M_CA S_B_N
M_W E_B _N
M_SC S_B_N0
F 26 | D D R 1_MA_15 | ||
H 26 | |||
D D R 1_MA_14 | |||
B 14 | |||
E 24 | D D R 1_MA_13 | ||
D D R 1_MA_12 | |||
E 23 | |||
H 14 | D D R 1_MA_11 | ||
D D R 1_MA_10 | |||
G 24 | |||
E 22 | D D R 1_MA_9 | ||
D D R 1_MA_8 | |||
D 22 | |||
J 27 | D D R 1_MA_7 | ||
D D R 1_MA_6 | |||
F 22 | |||
K 28 | D D R 1_MA_5 | ||
D D R 1_MA_4 | |||
L28 | |||
J 17 | D D R 1_MA_3 | ||
D D R 1_MA_2 | |||
J 16 | |||
J 14 | D D R 1_MA_1 | ||
D D R 1_MA_0 | |||
H 27 | |||
D D R 1_B A_2 | |||
K 13 | |||
D D R 1_B A_1 | |||
C 18 | |||
D D R 1_B A_0 | |||
G 14 | |||
D D R 1_R AS * | |||
E 14 |
| ||
| D D R 1_C AS * | ||
G 13 |
| ||
D D R 1_W E* | |||
D 12 | |||
D D R 1_C S_0 * | |||
D D R 0_MA_15
D D R 0_MA_14 D D R 0_MA_13
D D R 0_MA_12 D D R 0_MA_11
D D R 0_MA_10 D DR 0_MA _9
D DR 0_MA _8 D DR 0_MA _7
D DR 0_MA _6 D DR 0_MA _5
D DR 0_MA _4
D DR 0_MA _3
D DR 0_MA _2
D DR 0_MA _1
D DR 0_MA _0
D D R 0_BA _2
D D R 0_BA _1
D D R 0_BA _0
D DR 0_RA S*
D DR 0_CA S* 
D D R0_W E*
B29
A28
A10
B26
A26
B19
C26
B25
A25
C24
B24
B23
D24
C23
B21
A20
C28
A16
B16
A15
C12
B13
G15
M_MAA _A 15
M_MAA _A 14
M_MAA _A 13
M_MAA _A 12
M_MAA _A 11
M_MAA _A 10
M_MAA _A 9
M_MAA _A 8
M_MAA _A 7
M_MAA _A 6
M_MAA _A 5
M_MAA _A 4
M_MAA _A 3
M_MAA _A 2
M_MAA _A 1
M_MAA _A 0
M_S BS_A2
M_S BS_A1
M_S BS_A0
M_R AS _A _N
M_C AS _A _N
M_W E_A_N
M_S CS _A _N 0
J_C PU 1E
D D R 2_MA_1 5
D D R 2_MA_1 4
D D R 2_MA_1 3
D D R 2_MA_1 2
D D R 2_MA_1 1
D D R 2_MA_1 0
D D R2_MA_9
D D R2_MA_8
D D R2_MA_7
D D R2_MA_6
D D R2_MA_5
D D R2_MA_4
D D R2_MA_3
D D R2_MA_2
D D R2_MA_1
D D R2_MA_0
DD R 2_B A_2
DD R 2_B A_1
DD R 2_B A_0
D D R2_R AS*
D D R2_C AS*
D D R 2_W E*
D D R2_C S_0*
D D R2_C S_1*
D D R2_C S_2*
G25 H 24
F15
G23
H 23 H 17
H 22 L25
J 24 K22
K23
F20
J 20 G18
K17
A18
L26
F17
A17
D 17 F16 C 16
G16 |
K14 |
D 16 |
M_MA A_C15
M_MA A_C14
M_MA A_C13
M_MA A_C12
M_MA A_C11
M_MA A_C10
M_MA A_C9
M_MA A_C8
M_MA A_C7
M_MA A_C6
M_MA A_C5
M_MA A_C4
M_MA A_C3
M_MA A_C2
M_MA A_C1
M_MA A_C0
M_SBS_C 2
M_SBS_C 1
M_SBS_C 0
M_RA S_C_ N
M_CA S_C_ N
M_WE _C _N
M_SC S_C_N 0
M_SC S_C_N 1
Z0339
Sheet 3 of 47
ChannelB
M_SC S_B_N1 Z0301
Z0302
A8 | D D R 1_C S_1 * | |
E 15 | ||
D D R 1_C S_2 * | ||
E 13 | ||
|
DD R 0_C S _1* |
DD R 0_C S _2* |
B10
C13
B9
M_S CS _A _N 1
Z 0320 |
Z 0321 |
D D R2_C S_3* D D R2_C S_4*
H 16 |
E17
D 9 |
Z0340
Z0341
Z0342
LGA1366 Part B
DDR3
2/2
8M_MAA_B[ 15: 0]
8M_SB S_B[2: 0]
8M_SC KE _B [1: 0]
8M_OD T_B[ 1:0]
8CK _M_C H1_0 _D P
8CK _M_C H1_0 _D N
8CK _M_C H1_1 _D P
8CK _M_C H1_1 _D N
CK_M_CH1_2_DP CK_M_CH1_2_DN CK_M_CH1_3_DP CK_M_CH1_3_DN
8M_R AS_B_N
8M_C AS_B_N
8M_W E_B_N
8M_SC S_B_N 0
8M_SC S_B_N 1
M_SCS_B_N4
M_SCS_B_N5
8 DD R 1_D R AMR ST
M_MA A_B[15:0]
M_S BS_B[ 2:0]
M_S C KE_B[ 1: 0]
M_OD T_B[1: 0]
C K_M_C H 1_0_ DP C K_M_C H 1_0_ DN
C K_M_C H 1_1_ DP C K_M_C H 1_1_ DN
DIMM1 no using
M_R A S_B_N
M_C A S_B_N
M_W E _B _N
M_S C S_B_N 0
M_S C S_B_N 1
DIMM1 no using
D D R1_D RA MR ST
Z0303
Z0304
Z0305
Z0306
C K_M_C H 1_0 _ D P C K_M_C H 1_0 _ D N C K_M_C H 1_2 _ D P
C K_M_C H 1_2 _ D N C K_M_C H 1_1 _ D P
C K_M_C H 1_1 _ D N C K_M_C H 1_3 _ D P C K_M_C H 1_3 _ D N
M_SC KE_B0
Z0307
M_SC KE_B1
Z0308
Z0309
Z0310
Z0311
Z0312
Z0313
Z0314
M_OD T_B1
M_OD T_B0
|
| D D R 1_C S_3 * | |
C 17 | |||
| D D R 1_C S_4 * | ||
E 10 |
| ||
| D D R 1_C S_5 * | ||
C 14 |
| ||
| D D R 1_C S_6 /O D T_4* | ||
E 12 |
| ||
| D D R 1_C S_7 /O D T_5* | ||
C 21 |
| ||
| D D R 1_C LK_ P0 | ||
D 21 |
| ||
| D D R 1_C LK_ N 0 | ||
G 19 |
| ||
| D D R 1_C LK_ P1 | ||
G 20 |
| ||
K 18 |
| D D R 1_C LK_ N 1 | |
| D D R 1_C LK_ P2 | ||
L18 |
| ||
H 18 |
| D D R 1_C LK_ N 2 | |
| D D R 1_C LK_ P3 | ||
H 19 |
| ||
H 28 |
| D D R 1_C LK_ N 3 | |
| D D R 1_C KE _0 | ||
E 27 |
| ||
D 27 |
| D D R 1_C KE _1 | |
| D D R 1_C KE _2 | ||
C 27 |
| ||
|
| D D R 1_C KE _3 |
G 28
H 29 R S VD _G 28 R S VD _H 29
E 28 | R S VD _E 28 | |
F 28 | ||
R S VD _F 28 | ||
F 11 | ||
D D R 1_O D T_3 | ||
D 14 | ||
D D R 1_O D T_2 | ||
C 8 | ||
D D R 1_O D T_1 | ||
D 11 | D D R 1_O D T_0 |
DD R 0_C S _3* |
DD R 0_C S _4* |
DD R 0_C S _5* |
D D R 0_C S_6 /OD T_4* 
D D R 0_C S_7 /OD T_5*
D DR 0_CLK_ P0 D D R 0_C LK_ N0
D DR 0_CLK_ P1 D D R 0_C LK_ N1
D DR 0_CLK_ P2 D D R 0_C LK_ N2
D DR 0_CLK_ P3 D D R 0_C LK_ N3
DD R 0_C KE _0
DD R 0_C KE _1
DD R 0_C KE _2 DD R 0_C KE _3
RS VD _A 31
R SVD _C 32
R SVD _C 31
R SVD _D 31
DD R 0_O D T_3 |
DD R 0_O D T_2 |
DD R 0_O D T_1 |
B15
A7
C11
B8
J19
K19
D19
C19
F18
E18
E20
E19
C29
A30
B30
B31
A31
C32
C31
D31
C7
B11
C9
Z 0322 |
Z 0323 |
Z 0324 |
Z 0325 |
C K_M_CH 0_ 0_ D P C K_M_CH 0_ 0_ D N C K_M_CH 0_ 2_ D P C K_M_CH 0_ 2_ D N
C K_M_CH 0_ 1_ D P C K_M_CH 0_ 1_ D N C K_M_CH 0_ 3_ D P C K_M_CH 0_ 3_ D N
M_S CK E_A0
Z 0326
M_S CK E_A1
Z 0327
Z0328 Z 0329
Z0330 Z 0331
Z0332 Z 0333
M_OD T_A 1
D D R2_C S_5*
DD R 2_C S_6 /OD T_4* DD R 2_C S_7 /OD T_5*
D D R 2_C LK _P 0
DD R 2_C LK_N 0
D D R 2_C LK _P 1
DD R 2_C LK_N 1
D D R 2_C LK _P 2
DD R 2_C LK_N 2
D D R 2_C LK _P 3
DD R 2_C LK_N 3
D DR 2_CK E_0
D DR 2_CK E_1
D DR 2_CK E_2
D DR 2_CK E_3
R SVD _K27
R SV D_D 30
R SVD _K29
R SV D _J 29 D DR 2_OD T_3
D DR 2_OD T_2 D DR 2_OD T_1
D DR 2_OD T_0 DD R 2_MA_PA R
D D R 2_PAR _ER R _0* D D R 2_PAR _ER R _1*
L17 |
J 15 |
J 22
J 21 L20
K20 H 21
G21 L22 L21
J 26 G26
D 26 L27
K27
D 30 K29
J 29 D 10
D 15 F13
L16
B18
F21
J 25 |
Z0343
Z0344
CK _M_C H2_0 _D P
CK _M_C H2_0 _D N CK _M_C H2_2 _D P CK _M_C H2_2 _D N
CK _M_C H2_1 _D P
CK _M_C H2_1 _D N
CK _M_C H2_3 _D P CK _M_C H2_3 _D N
M_SC KE_C 0
Z0345
M_SC KE_C 1
Z0346
Z0347
Z0348
Z0349
Z0350
Z0351
Z0352
M_OD T_C1
M_OD T_C0
Z0353
Z0354
Z0355
B.Schematic Diagrams
ChannelC
DD R 0_O D T_0 |
F12
M_OD T_A 0
D D R 2_PAR _ER R _2* R SVD _K25*
F23 |
K25
Z0356
Z0357
9M_MAA_C [ 15: 0]
9M_SB S_C[ 2:0]
9M_SC KE _C [ 1:0]
9M_OD T_C [ 1: 0]
9CK _M_C H2_0 _D P
9CK _M_C H2_0 _D N
9CK _M_C H2_1 _D P
9CK _M_C H2_1 _D N
CK_M_CH2_2_DP CK_M_CH2_2_DN CK_M_CH2_3_DP CK_M_CH2_3_DN
9 M_R AS_C _N |
M_MA A_C[ 15: 0]
M_S BS_C [2: 0]
M_S C KE_C [1: 0]
M_OD T_C[ 1:0]
C K_M_C H 2_0_ DP C K_M_C H 2_0_ DN
C K_M_C H 2_1_ DP C K_M_C H 2_1_ DN
DIMM1 no using
M_R A S_C_N
Z0315
Z0316
Z0317
Z0318
Z0319
D D R _C OMP1
D D R 1_D R AMRS T
D 20 | D D R 1_MA_PA R |
| ||
C 22 |
|
| ||
| D D R 1_P AR _E RR _ 0* | |||
E 25 | ||||
D D R 1_P AR _E RR _ 1* | ||||
F 25 |
| |||
| D D R 1_P AR _E RR _ 2* | |||
F 27 |
| |||
R S VD _F 27 |
| |||
Y 7 |
| |||
D D R _COMP_1 |
| |||
D 29 |
| |||
D D R 1_R ES ET* | LG A1 3 66 | |||
|
| |||
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| ||
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| 4 OF 12 | |
D D R 0_MA_PAR
D DR 0_PAR _ER R _0* 
D DR 0_PAR _ER R _1*
D DR 0_PAR _ER R _2* 
R S VD _B 33*
D D R_C O MP _0
D DR 0_RE SET* 
B20
D25
B28
A27
B33
AA8
D32
Z 0334
Z0335
Z 0336 Z 0337 Z 0338
D D R _C OMP0
D D R 0_D R AMR ST
| D D R _C OMP_2 |
LG A1 36 6 | D D R 2_R ESE T* |
| |
5 OF 12 |
|
AC 1
E32
DD R _COMP2
DD R 2_D R AMR ST
9 | M_C AS_C _N |
9 | M_W E_C _N |
9M_SC S_C _N0
9M_SC S_C _N1
M_SCS_C_N5
M_SCS_C_N6
9 DD R 2_D R AMR ST
M_C A S_C_N
M_W E _C _N
M_S C S_C_N 0
M_S C S_C_N 1
DIMM1 no using
D D R2_D RA MR ST
5 m ils Trac e w idt h | DD R _COMP0 | R2 | 42 | 1 | 00 _ 1%_04 | ||
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| |
1500mils max t rac e lengt h |
| 43 |
| 2 | 4. 9_ 1% _04 | ||
| DD R _COMP1 R2 |
| |||||
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| DD R _COMP2 | R3 | 1 |
| 1 | 30_ 1%_04 | |
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