Cypress CY14B101Q1, CY14B101Q2, CY14B101Q3 nvSRAM Special Instructions

PRELIMINARY

CY14B101Q1

CY14B101Q2

CY14B101Q3

Document #: 001-50091 Rev. *A Page 11 of 22

nvSRAM Special Instructions

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four

special instructions which enables access to four nvSRAM

specific functions: STORE, RECALL, ASDISB, and ASENB.

Tabl e 8 lists these instructions.

Software STORE

When a STORE instruction is executed, nvSRAM performs a

Software STORE operation. The STORE operation is issued

irrespective of whether a write has taken place since last STORE

or RECALL operation.

To issue this instruction, the device must be write enabled (WEN

bit = ‘1’). The instruction is performed by transmitting the STORE

opcode on the SI pin following the falling edge of CS. The WEN

Figure 12. Burst Mode Read Instruction Timing

Figure 13. Write Instruction Timing

Figure 14. Burst Mode Write Instruction Timing

SCK

LSB

Op-Code

17-bit Address

MSB LSB

012 3 456 7 0765432

120 21 22 23 01234567 01234567

00000011 0 0 00 00 0

A16 A3 A2 A1 A0

D2D3

Data Byte 1 Data Byte N

MSB LSB

MSB

D2D3

D7 D0D7

SCK

012345 6 7 076543212021222301234567

MSB LSB

Data

D0D1D2D3D4D5D6D7

Op-Code

0000001 00000000A16 A3 A1A2 A0

17-bit Address

MSB LSB

HI-Z

SCK

MSB LSB

Op-Code

17-bit Address

MSB LSB

01234567

076 5 432

120 21 22 23 01234567 01234567

000000

100000000

A16 A3 A2 A1 A0

HI-Z

Data Byte 1 Data Byte N

D2D3

D7 D0D7

Cypress CY14B101Q1, CY14B101Q2, CY14B101Q3 nvSRAM Special Instructions

Document #: 001-50091 Rev. *A Page 11 of 22

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four

special instructions which enables access to four nvSRAM

specific functions: STORE, RECALL, ASDISB, and ASENB.

Tabl e 8 lists these instructions.

Software STORE

When a STORE instruction is executed, nvSRAM performs a

Software STORE operation. The STORE operation is issued

irrespective of whether a write has taken place since last STORE

or RECALL operation.

To issue this instruction, the device must be write enabled (WEN

bit = ‘1’). The instruction is performed by transmitting the STORE

opcode on the SI pin following the falling edge of CS. The WEN

Figure 12. Burst Mode Read Instruction Timing

Figure 13. Write Instruction Timing

Figure 14. Burst Mode Write Instruction Timing

LSB

MSB LSB

Data Byte 1 Data Byte N

MSB LSB

MSB

HI-Z

HI-Z

Data Byte 1 Data Byte N

Table 8. nvSRAM Special Instructions

Function Name Opcode Operation

STORE 0011 1100 Software STORE

RECALL 0110 0000 Software RECALL

ASENB 0101 1001 AutoStore Enable

ASDISB 0001 1001 AutoStore Disable

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