CY14B101Q1

CY14B101Q2

PRELIMINARYCY14B101Q3

AutoStore or Power Up RECALL

Parameters

 

 

Description

CY‘4B101QxA

Unit

 

 

Min

Max

 

 

 

 

 

tFA [7]

 

Power Up RECALL Duration

 

20

ms

tSTORE [8]

 

STORE Cycle Duration

 

8

ms

tDELAY [9]

 

Time Allowed to Complete SRAM Cycle

 

25

ns

VSWITCH

 

Low Voltage Trigger Level

 

2.65

V

tVCCRISE

 

VCC Rise Time

150

 

μs

VHDIS[6]

 

HSB

Output Driver Disable Voltage

 

1.9

V

tLZHSB

 

HSB

To Output Active Time

 

5

μs

tHHHD

 

HSB

High Active Time

 

500

ns

Switching Waveforms

Figure 23. AutoStore or Power Up RECALL[10]

VSWITCH

VHDIS

HSB OUT

Autostore

POWER-UP

RECALL

Read and Write Inhibited (RWI)

VVCCRISE

 

Note8

tSTORE

Note8

tSTORE

 

tHHHD

 

 

 

tHHHD

Note11

 

 

 

 

 

 

 

 

 

 

tDELAY

 

 

tLZHSB

 

 

 

tLZHSB

 

 

 

tDELAY

 

 

 

 

 

tFA

 

 

 

tFA

 

POWER-UP

Read and Write

BROWN

POWER-UP

Read and Write

POWER

RECALL

 

OUT

 

RECALL

 

DOWN

 

 

AUTOSTORE

 

AUTOSTORE

Notes

7.tFA starts from the time VCC rises above VSWITCH.

8.If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated

9.On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

10.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

11.HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-50091 Rev. *A

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Cypress CY14B101Q1 AutoStore or Power Up Recall, Switching Waveforms, Parameters Description CY‘4B101QxA Unit Min Max