PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3

Document #: 001-50091 Rev. *A Page 16 of 22

AutoStore or Power Up RECALL

Parameters Description CY‘4B101QxA Unit

Min Max

tFA [7] Power Up RECALL Duration 20 ms

tSTORE [8] STORE Cycle Duration 8ms

tDELAY [9] Time Allowed to Complete SRAM Cycle 25 ns

VSWITCH Low Voltage Trigger Level 2.65 V

tVCCRISE VCC Rise Time 150 μs

VHDIS[6] HSB Output Driver Disable Voltage 1.9 V

tLZHSB HSB To Output Active Time 5 μs

tHHHD HSB High Active Time 500 ns

Switching Waveforms
Figure 23. AutoStore or Power Up RECALL[10]
tSTORE
tSTORE
tHHHD
tHHHD
tDELAY
tDELAY
VVCCRISE Note8Note8
Note11
tLZHSB tLZHSB
tFA tFA
VSWITCH
VHDIS
HSB OUT
Autostore
POWER-UP
RECALL
Read and Write
Inhibited (RWI)
POWER-UP
RECALL
POWER-UP
RECALL
Read and Write Read and Write
BROWN
OUT
AUTOSTORE
POWER
DOWN
AUTOSTORE
Notes
7. tFA starts from the time VCC rises above VSWITCH.
8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated
9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY
.
10.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
11. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
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