Hardware Store Cycle

			CY14B101Q1
			CY14B101Q1
		PRELIMINARY	CY14B101Q2
		PRELIMINARY	CY14B101Q3

Parameter		Description	CY14B101Q1		Unit
			Min	Max

tDHSB		To Output Active Time when write latch not set		25	ns
	HSB
tPHSB	Hardware STORE Pulse Width		15		ns

Switching Waveforms

Write Latch set

tPHSB

HSB (IN)

tDELAY

HSB (OUT)

RWI

Figure 26. Hardware STORE Cycle[8]

~ ~
tSTORE	~
~~	~
	~

tHHHD

tLZHSB

Write Latch not set

tPHSB

HSB (IN)

HSB	(OUT)	tDELAY
		tDELAY
RWI

~ ~

tDHSB

HSB pin is driven high to VCC only by Internal 100K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

tDHSB

~ ~

Document #: 001-50091 Rev. *A

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Cypress CY14B101Q3, CY14B101Q2 Hardware Store Cycle, Parameter Description CY14B101Q1 Unit Min, Hardware Store Pulse Width

Contents

Functional Overview FeaturesLogic Block Diagram Mbit NonVolatile Sram Internally organized as 128K x Pinouts Pin Definitions Pin Name Type DescriptionHold Sram Read Device OperationSram Write Store Operation Hardware Store and HSB pin Operation Hardware Recall Power UpSoftware Store Operation Recall Operation Serial Peripheral Interface SPI Overview System Configuration Using SPI nvSRAM SPI Modes SPI Operating Features SPI Functional Description Status Register Read Status Register Rdsr InstructionWrite Status Register Wrsr Instruction Write Protection and Block Protection Write Enable Wren InstructionWrite Disable Wrdi Instruction Block Protection Read Sequence Read Memory AccessWrite Protect WP Pin Write Sequence Write NvSRAM Special Instructions Software StoreNvSRAM Special Instructions Function Name Opcode Operation AutoStore Disable Asdisb AutoStore Enable AsenbHold Pin Operation Operating Range DC Electrical CharacteristicsMaximum Ratings Parameter Description Test Conditions Min Max Unit Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions AC Switching Characteristics Cypress Alt Description 40MHz Unit Parameter Min Max AutoStore or Power Up Recall Switching WaveformsParameters Description CY‘4B101QxA Unit Min Max Recall Duration 200 Software Controlled Store and Recall CyclesParameter Description CY14B101Q1 Unit Min Max Soft Sequence Processing Time 100 Parameter Description CY14B101Q1 Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width Part Numbering Nomenclature Ordering Code Package Package Type Operating Diagram RangeOrdering Information CY 14 B 101 Q 1-SF X C T Package Diagrams Pin 300 mil DFN Package Pin 300 mil Soic Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no

PRELIMINARY

CY14B101Q3

Hardware STORE Cycle

Parameter

Description

CY14B101Q1

Unit

Min

To Output Active Time when write latch not set

Hardware STORE Pulse Width

Switching Waveforms

Figure 26. Hardware STORE Cycle[8]