PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document #: 001-50091 Rev. *A Page 15 of 22
AC Switching Characteristics
Cypress
Parameter
Alt.
Parameter Description 40MHz Unit
Min Max
fSCK fSCK Clock Frequency, SCK 40 MHz
tCL tWL Clock Pulse Width Low 11 ns
tCH tWH Clock Pulse Width High 11 ns
tCS tCE CS High Time 20 ns
tCSS tCES CS Setup Time 10 ns
tCSH tCEH CS Hold Time 10 ns
tSD tSU Data In Setup Time 5 ns
tHD tHData In Hold Time 5 ns
tHH tHD HOLD Hold Time 5 ns
tSH tCD HOLD Setup Time 5 ns
tCO tVOutput Valid 9 ns
tHHZ tHZ HOLD to Output High Z 15 ns
tHLZ tLZ HOLD to Output Low Z 15 ns
tOH tHO Output Hold Time 0 ns
tHZCS tDIS Output Disable Time 25 ns
Figure 21. Synchronous Data Timing (Mode 0)
Figure 22. HOLD Timing
HI-Z
VALID IN
HI-Z
CS
SCK
SI
SO
tCL
tCH
tCSS
tSD tHD
tCO tOH
tCS
tCSH
tHZCS
CS
SCK
HOLD
SO
tSH
tHHZ tHLZ
tHH
tSH
tHH
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