CY14B256K

Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock

Document Number: 001-06431

Rev.

ECN

Orig. of Change

Submission

Description of Change

Date

 

 

 

 

 

 

 

 

 

 

 

*H

2663934

GVCH/PYRS

02/24/09

Updated Features section

 

 

 

 

Updated pin definition of

WE

pin

 

 

 

 

Updated “Reading the clock”, “Backup Power”, “Stopping and

 

 

 

 

starting the Oscillator” and “Alarm” descriptions under RTC

 

 

 

 

operation

 

 

 

 

Modified “Figure 4. RTC Recommended Component Configuration”

 

 

 

 

Added footnote 4

 

 

 

 

Added footnote 6

 

 

 

 

Added default values to RTC Register Map” table

 

 

 

 

Updated flag register description in Register Map Detail” table

 

 

 

 

Added Industrial specs for 25ns and 35ns speed

 

 

 

 

Changed VIH from vcc+0.3 to Vcc+0.5

 

 

 

 

Added “Data Retention and Endurance” table on page 15

 

 

 

 

Added thermal resistance values

 

 

 

 

Added alternate parameters in the AC switching characteristics

 

 

 

 

table

 

 

 

 

Renamed tOH to tOHA

 

 

 

 

Changed tHRECALL from 20 to 40ms

 

 

 

 

Changed tRECALL spec from 100μs to 170μs (Including tss of 70us)

 

 

 

 

Renamed tAS to tSA

 

 

 

 

Renamed tGHAX to tHA

 

 

 

 

Renamed tHLHX to tPHSB

 

 

 

 

Updated Figure 16

 

 

 

 

Added truth table for SRAM operations

 

 

 

 

 

 

 

Document Number: 001-06431 Rev. *H

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Cypress CY14B256K 2663934, Updated Features section, Pin, Updated Reading the clock, Backup Power, Stopping, Operation