CY14B256K
tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated, the CY14B256K continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14B256K remains disabled until the HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC<VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B256K software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further READs and WRITEs are inhibited untill the cycle is completed.
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If it intervenes, the sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ sequence is performed:
1.Read address 0x0E38, Valid READ
2.Read address 0x31C7, Valid READ
3.Read address 0x03E0, Valid READ
4.Read address 0x3C1F, Valid READ
5.Read address 0x303F, Valid READ
6.Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled.
It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for READ and WRITE operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed:
1.Read address 0x0E38, Valid READ
2.Read address 0x31C7, Valid READ
3.Read address 0x03E0, Valid READ
4.Read address 0x3C1F, Valid READ
5.Read address 0x303F, Valid READ
6.Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements.
Data Protection
The CY14B256K protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH.
If the CY14B256K is in a WRITE mode (both CE and WE are low) at power up after a RECALL, or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
The CY14B256K is a high speed memory and must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Document Number: | Page 4 of 28 |
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