CY14B256K
Pin Configurations
Figure 1. 48-Pin SSOP
VCAP
NC
A14
A12
A7
A6
A5
INT
A4
NC
NC
NC
VSS
NC
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
X1
X2
1
2
3
4
5
6
7
8
9
1048-SSOP
11
12Top View
13
14(Not To Scale)
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
NC
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
VRTCcap
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Pin Definitions
Pin Name | Alt | IO Type |
|
| Description |
| ||||||||||||||||
|
|
|
|
|
|
| Input | Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. |
| |||||||||||||
|
|
|
|
|
|
| Input or Output | Bidirectional Data IO lines. Used as input or output lines depending on operation. | ||||||||||||||
|
| NC |
|
|
|
|
|
|
| No Connect | No Connects. This pin is not connected to the die. |
| ||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| Input | Write Enable Input, Active LOW. When the chip is enabled and |
| is LOW, data on the IO | |||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| WE | ||||||||
|
| WE | W | |||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| pins is written to the specific address location. |
| ||||||
|
|
|
|
|
|
|
|
|
|
|
| Input | Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. | |||||||||
|
| CE |
| E | ||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| Input | Output Enable, Active LOW. The active LOW |
| input enables the data output buffers during | |||||
|
|
|
|
|
|
|
|
|
|
|
| OE | ||||||||||
|
| OE |
| G | ||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| read cycles. Deasserting OE high causes the IO pins to |
| ||||||
|
| X1 |
|
|
|
|
|
|
| Output | Crystal Connection. Drives crystal on start up. |
| ||||||||||
|
| X2 |
|
|
|
|
|
|
| Input | Crystal Connection for 32.768 kHz Crystal. |
| ||||||||||
VRTCcap |
|
|
|
|
|
|
| Power Supply | Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used) | |||||||||||||
VRTCbat |
|
|
|
|
|
|
| Power Supply | Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used) | |||||||||||||
|
| INT |
|
|
|
|
|
|
| Output | Interrupt Output. It is programmed to respond to the clock alarm, the watchdog timer, and the | |||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain). | |||||||
| VSS |
|
|
|
|
|
|
| Ground | Ground for the Device. It is connected to ground of the system. |
| |||||||||||
| VCC |
|
|
|
|
|
|
| Power Supply | Power Supply Inputs to the Device. |
| |||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| Input or Output | Hardware Store Busy | (HSB) | . When low, this output indicates a Hardware Store is in progress. | |||||
| HSB |
|
|
|
|
|
|
| ||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal | |||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| pull up resistor keeps this pin HIGH if not connected (connection optional). |
| ||||||
VCAP |
|
|
|
|
|
|
| Power Supply | AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM | |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| to nonvolatile elements. |
| ||||||
Document Number: | Page 2 of 28 |
[+] Feedback